Easy Testbench Speedups
As a Doulos ‘techie’, I train over 100 engineers in SystemVerilog and UVM each year. I do believe quite soundly, that the effort of simulation verification is an art, supported by the language. So, regardless of the language, I have a ready list of useful testbench coding strategies to achieve faster regression CPU cycle execution. This means more regression tests executed in the same amount of ‘wall-clock’ time!
![](https://res.cloudinary.com/dlzix82l9/image/upload/f_auto/v1708128439/Verification-Horizons/July-2022/verification-horizons_easy-testbench-speedups_pcobgn.jpg)
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