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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

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    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

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      • Introduction to ISO 26262
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    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
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    • Formal-Based Techniques

      • Formal Assertion-Based Verification
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      • Handling Inconclusive Assertions in Formal Verification
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    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

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    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

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    • Coverage Cookbook

      • Introduction
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  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

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  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

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  • Home
  • Verification Horizons
  • July 2022
  • Getting to Know Visualizer, Part II

Getting to Know Visualizer, Part II

Verification Horizons - Tom Fitzpatrick, Editor

by Rich Edelman - Siemens EDA

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Welcome to part 2 of our overview of the Visualizer Debug Environment, the user interface to debug, analyze and verify all our Siemens functional verification tools.

As we saw in part 1, Visualizer is first and foremost a waveform debugger, with a host of other powerful debug capabilities also provided and supporting Verilog, SystemVerilog, VHDL, System C and C/C++. In this part of the article, we’ll look at driver tracing, X tracing, schematics, glitch debug, low power debug and coverage analysis and coverage debug – all It supports debugging simulation with Questasim, emulation with Veloce and prototyping with VPS.

Visualizer supports live simulation debug and post simulation debug.

DRIVER TRACING

Driver Tracing by Double Clicking

...

Table of Contents

Verification Horizons Articles:

  • Successful Planning Entails Establishing Precise Goals and Securing Adequate Resources

  • Back to the Future with Formal Property Checking

  • Getting to Know Visualizer, Part II

  • The Democratization of Digital Methodologies for AMS Verification

  • Unblocking the Full Potential of SSDs Using Zoned and Key Value Namespaces

  • Bringing 5G NR Radio Frame Generation and Analysis to the Veloce® X-STEP™ Product Family

  • Speeding OTN Verification Using Emulation

  • Reflections on Users’ Experiences with SVA, Part II

  • Easy Testbench Speedups

  • Functional Safety Verification Challenges for Automotive ICs

  • The Path to a Safety Mechanism on an Unsafe PCIe® Sub-Module Using Siemens EDA Austemper

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