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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

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    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

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      • Introduction to ISO 26262
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    • Additional Courses

      • Assertion-Based Verification
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      • Formal Assertion-Based Verification
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    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

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    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

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    • Coverage Cookbook

      • Introduction
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  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

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      • View all Xcelerator Academy classes
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

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  • Home
  • Verification Horizons
  • July 2022
  • Bringing 5G NR Radio Frame Generation and Analysis to the Veloce® X-STEP™ Product Family

Bringing 5G NR Radio Frame Generation and Analysis to the Veloce® X-STEP™ Product Family

Verification Horizons - Tom Fitzpatrick, Editor

by Yrjö Keränen - Siemens EDA

Please login to view the entire Verification Horizons article.

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Booming worldwide development activities for 5G NR create an increasing need for reference data and signal analysis. Recently launched Veloce X-STEP IQ Toolset (IQT) provides 3GPP compliant test data for radio unit (RU) testing needs. IQT workflow integrates with Siemens EDA tools such as Questa, Veloce and X-STEP. Being a standalone software solution, it is a cost-efficient solution to be installed in multiple workstations. Typical uses include driving RU transmission with 3GPP Test Models and analyzing captured reception containing 3GPP Fixed Reference Channel (FRC) transmission.

BACKGROUND

Introduction of 5G New Radio (NR) and its continuing development, have in recent years increased the number of companies developing cellular network

...

Table of Contents

Verification Horizons Articles:

  • Successful Planning Entails Establishing Precise Goals and Securing Adequate Resources

  • Back to the Future with Formal Property Checking

  • Getting to Know Visualizer, Part II

  • The Democratization of Digital Methodologies for AMS Verification

  • Unblocking the Full Potential of SSDs Using Zoned and Key Value Namespaces

  • Bringing 5G NR Radio Frame Generation and Analysis to the Veloce® X-STEP™ Product Family

  • Speeding OTN Verification Using Emulation

  • Reflections on Users’ Experiences with SVA, Part II

  • Easy Testbench Speedups

  • Functional Safety Verification Challenges for Automotive ICs

  • The Path to a Safety Mechanism on an Unsafe PCIe® Sub-Module Using Siemens EDA Austemper

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