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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

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    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

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    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

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    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

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    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

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  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

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      • View all Xcelerator Academy classes
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

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  • Home
  • Verification Horizons
  • July 2022
  • Unblocking the Full Potential of SSDs Using Zoned and Key Value Namespaces

Unblocking the Full Potential of SSDs Using Zoned and Key Value Namespaces

Verification Horizons - Tom Fitzpatrick, Editor

by Himani Kaushik - Siemens EDA

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INTRODUCTION

Since the advent of digitalization, there has been an exponential growth in the volume of data. With this boost in the amount of data, hard disk drives (HDDs) could not sustain the data transfer rates, leading to bottlenecks in data access. Solid state drives (SSDs) have come to the forefront as a promising solution to our modern-day storage demands. SSDs are constantly evolving with upgrades of their critical components to provide high access speeds. One such component is created by the division of non-volatile memory (NVM), commonly known as namespaces, for the NVMe specification.

Namespaces are perceived as formatted logical blocks that kick-start block storage in SSDs. Each block in a typical flash chip consists of many

...

Table of Contents

Verification Horizons Articles:

  • Successful Planning Entails Establishing Precise Goals and Securing Adequate Resources

  • Back to the Future with Formal Property Checking

  • Getting to Know Visualizer, Part II

  • The Democratization of Digital Methodologies for AMS Verification

  • Unblocking the Full Potential of SSDs Using Zoned and Key Value Namespaces

  • Bringing 5G NR Radio Frame Generation and Analysis to the Veloce® X-STEP™ Product Family

  • Speeding OTN Verification Using Emulation

  • Reflections on Users’ Experiences with SVA, Part II

  • Easy Testbench Speedups

  • Functional Safety Verification Challenges for Automotive ICs

  • The Path to a Safety Mechanism on an Unsafe PCIe® Sub-Module Using Siemens EDA Austemper

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