Verification Academy Live in Silicon Valley - Avery Verification IP for AI/ML/HPC

Registration and Check-in

Coffee and networking with your peers.

Welcome and Introductions

Nidhi Jain | AE Manager, Functional Verification

Keynote: At the Speed of AI: Keep pace with AI chip development using AI EDA tools

Abhi Kolpekwar | VP & GM, Digital Verification Technologies Division

AI technology is moving rapidly. The chip hardware requirement for processing power, storage, and communication is moving off the charts, and EDA has accepted the challenge to keep up and to provide scale-up solutions. We see the industry urgently looking for advancements in communication protocols for scale-up and scale-out in the AI/ML datacenter, such as Ultra Accelerator Link (UALink), Ultra Ethernet (UEC), and PCIe Gen7, which are needed by any AI/ML design in 2025. We describe our solutions for Verification and Signoff in this space and describe how we are investing with AI/ML technology in new Questa One productivity tools to enable teams to work with the most complex designs.

Verifying Future Accelerator Interconnects: UALink™ Verification IP and Why UALink Matters

One of our UALink customers presents alongside Jalaj Gupta | Product Engineering Lead

UALink™ is a critical open interconnect standard designed to deliver bandwidth, low latency, and interoperability required by next-generation AI and accelerator systems. As UALink designs grow in complexity, comprehensive verification is essential to ensure protocol compliance, robustness, and multi-vendor interoperability.

This presentation highlights the importance of UALink and the verification challenges it introduces and shows how Avery UALink Verification IP delivers immediate value by accelerating bring-up, improving coverage of protocol corner cases, and reducing overall verification risk and time-to-market.

Panel: Ethernet and AI/ML standards wars

Industry experts from Siemens EDA Verification IP team and our customers/partners

AI/ML workloads are reshaping data center networking and intensifying competition among Ethernet-based and emerging interconnect standards. This panel explores the Ethernet and AI/ML standards wars, focusing on key technical tradeoffs, ecosystem dynamics, and implications for scaling AI systems. Attendees will gain perspective on where standards are converging, where fragmentation persists, and what it means for the future of AI networking.

Lunch and Networking

Verifying Chiplet Interconnects at Scale: UCIe® 3.0

Luis Rodriguez | Engineering Site Lead

UCIe® has become the foundation for open, interoperable chiplet-based designs, and UCIe 3.0 extends this vision with higher bandwidth, longer reach, and enhanced features to support advanced packaging and system scalability. As capabilities expand, verification complexity increases across protocol, performance, and interoperability dimensions. This presentation highlights what’s new in UCIe 3.0 and explains how Avery UCIe Verification IP enables faster bring-up, deeper protocol coverage, and reduced risk by validating compliance, corner cases, and system-level behavior—helping teams confidently deliver robust chiplet-based silicon.

Securing Next-Generation Interconnects: PCIe® Gen7 Security Verification

Jalaj Gupta | Product Engineering Lead

PCIe® Gen7 delivers unprecedented bandwidth and introduces stronger security capabilities, including TDISP for device security and isolation, and IDE for end-to-end data encryption and integrity. These features are critical for protecting data and establishing trust in modern, disaggregated, and chiplet-based systems, but they significantly increase verification complexity. This presentation highlights what’s new in PCIe Gen7 security and demonstrates how Avery Verification IP—built on deep PCIe and UCIe verification expertise—enables early validation of TDISP and IDE functionality, comprehensive protocol and security coverage, and faster compliance, reducing risk and time-to-market for secure PCIe designs.

Arm Neoverse CSS RTL Signoff with CSS VIP and Software Aware VIP

Luis Rodriguez | Engineering Site Lead

A robust methodology to accelerate the development and verification of Arm® Neoverse™ V3 Compute Subsystem (CSS)-based designs, with a shift-left in simulation and signoff using Avery Protocol VIP, CSS VIP, Software Aware VIP and Arm Fast Models. The approach supports early software bring-up, including full UEFI and Linux bootup, while validating the RTL design and complex protocols like PCIe7, CXL4, HBM, and UCIe3 in simulation for fastest turnaround time. Critical system behaviors are validated early, reducing integration risks, as design moves to later project stages using hardware emulation or prototyping for larger workload and stress tests.

Panel: How to get RTL signoff teams and Firmware teams to work together?

Industry experts from Siemens EDA Verification IP team and our customers/partners

EDA delivers many forms of “shift-left” to the industry where Time to Market is everything. Our customers are challenged because the worlds of RTL design/verification engineering and Firmware/Software engineering remain in separate teams, separate rooms, even separate continents. We will explore and debate ideas and solutions in this space.