Verification Academy Live: Austin Topgolf
This seminar discusses technologies and techniques you can adopt to increase your verification productivity. We will cover how the new AI/ML paradigm shift across the industry is enabling functional verification productivity gains with Questa One across the verification cycle including RTL creation, simulation, coverage closure, system-level verification and through DFT simulations.
Thursday, February 19, 2026 | 9:30 AM - 5:15 PM
Location
Topgolf
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Register Here.
This event is in-person only — there is no support for remote participation.
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Agenda
Details Time Registration and Check-in
Coffee and networking with your peers
9:30 am – 10:00 am Welcome and Introductions
Mel Pratt | Application Engineering Manager
10:00 am – 10:05 am Keynote “At the Speed of AI: RTL-Signoff in the Convergence Era”
Abhi Kolpekwar | Senior Vice-President & General Manager, Design Verification Technologies
10:05 am – 10:50 am Enhancing Productivity in Simulation-Based Functional Verification with Questa One
Sunil Sahoo | Product Manager – Simulation
Chandu Challapalli | Solutions ManagerQuesta™ One represents a next-generation smart verification solution designed to transform chip verification from a bottleneck into a competitive advantage. Built on principles of connected, data-driven, and scalable verification, Questa One unifies engines, workflows, and teams to deliver faster insights and higher confidence across simulation, static, formal, and coverage domains. By integrating AI-enhanced automation, predictive analytics, and unified debug and regression management, Questa One accelerates coverage closure, simplifies complex tasks, and boosts overall engineer productivity—enabling verification teams to achieve results that were previously out of reach.
11:00 am – 11:45 am Complimentary Lunch and Networking
11:45 am – 1:00 pm Introducing Questa One SFV - The Transformation of Static & Formal Powered by AI/ML
David Landoll | Product Manager – Creation, Static and Formal
In today's fast-paced development schedules, engineers are constantly balancing innovation with efficiency. Questa One SFV, powered by AI/ML, is designed to streamline workflows, eliminate steep learning curves, and accelerate adoption. Learn how SFV can integrate into your current flow and improve productivity.
1:00 pm – 1:45 pm Arm Neoverse CSS RTL Signoff with CSS VIP and Software Aware VIP
Luis Rodriguez | Engineering Site Lead
A robust methodology to accelerate the development and verification of Arm® Neoverse™ V3 Compute Subsystem (CSS)-based designs, with a shift-left in simulation and signoff using Avery Protocol VIP, CSS VIP, Software Aware VIP and Arm Fast Models. The approach supports early software bring-up, including full UEFI and Linux bootup, while validating the RTL design and complex protocols like PCIe7, CXL4, HBM, and UCIe3 in simulation for fastest turnaround time. Critical system behaviors are validated early, reducing integration risks, as design moves to later project stages using hardware emulation or prototyping for larger workload and stress tests.
1:45 pm - 2:30 pm Accelerating Verification Closure with Siemens DFT Verification Solutions
Jake Wiltgen | Solutions Manager
This session details how Siemens DFT-centric verification technology tackles these challenges by providing a unified platform streamlined to Tessent flows, delivering industry leading performance and enhanced user experience, and accelerating DFT verification closure while reducing cost and risk to reach DFT sign-off.
2:30 pm - 3:15 pm Topgolf Happy Hour & Networking
3:15 pm - 5:15 pm We look forward to seeing you!
Siemens Advanced Functional Verification Team
* The agenda is subject to change without notice. -
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