Verification Academy Live

Welcome to Verification Academy Live.

Improving productivity has become crucial for efficiently utilizing expensive human and grid resources in the functional verification process. Achieving the "done" state requires more than simulator performance - it demands a strategic focus on optimizing workflows, prioritizing tasks, and leveraging metrics to guide efforts. A productivity-driven approach ensures resources are deployed effectively, accelerating verification closure.

Learn the value of Continuous Integration during development and how Questa Design Solutions are ideally suited for implementation in CI flows. Discover the benefits of integrating CI early to enhance RTL quality and streamline development processes.

Learn about the effectiveness of enhancing security verification and improving the robustness of your hardware security verification through detailed explanations and runtime insights. Explore methods to protect against data corruption using formal security verification techniques.

Leverage the power of AI and ML! Smart Verification revolutionizes functional verification by using faster engines that complement traditional heuristics with machine learning. Allow engineers to be more productive with advanced creation, analysis, and debugging capabilities, while reducing workloads through predictive technologies that streamline and accelerate the verification process.

Welcome to Verification Academy Live.

This session will focus on the Siemens Avery UCIe Verification IP and the new UCIe2.0 features. Discover its capabilities in dynamic environment creation, including generating complex SiP topologies, portable traffic generation, error injection, and debugging all within a native SystemVerilog/UVM framework.

This session introduces Avery Verification IP for Ethernet 1.6T, UALink, and UEC, providing essential tools to verify complex designs for next-generation connectivity. You will gain insights into the key challenges and innovations in Ethernet 1.6T, the latest high-speed Ethernet standard, and learn how Avery's Verification IP accelerates design validation with comprehensive protocol coverage, scalability, and advanced debugging capabilities.

This session will delve into the advanced features of Avery’s PCIe Verification IP, including dynamic testbench creation, sophisticated traffic generation, error injection, and protocol compliance checks. Discover how this native SystemVerilog/UVM VIP enables rigorous testing of performance, power efficiency, and scalability, ensuring designs meet demands of next-generation PCIe applications. Guest Speaker: Ganesh Venkatakrishnan from Scaleflux presented his experience with the Avery PCIe VIP.

The Avery VIP team have created solutions in this space that can mix abstraction levels and software as stimulus for our SoC subsystem testbenches. We'll demonstrate how you can benefit from fast, productive verification, while in the simulation phase of your project, with our available Virtual In-Circuit Simulation VIP solutions.

In this session, discover how Siemens’ Avery Verification IP for HBM4 and LPDDR6 provides a scalable and customizable solution for rigorous protocol compliance and performance testing. Learn how our leading users leverage this VIP to verify their memory controller IP and subsystems, ensuring reliability and readiness for next-generation applications. Guest Speaker: Nidish Kamath from Rambus spoke about Rambus's HBM4 memory controller and the partnership with Avery memory VIP.

VIQ is a collaborative, browser-based, data-driven platform that revolutionizes the verification process. By harnessing the power of machine learning, VIQ delivers advanced analytics, enhanced collaboration capabilities, and comprehensive traceability. This innovative approach significantly boosts verification efficiency, empowering you to maximize your productivity.

Now that our acquisition of Avery Design Systems is complete, Siemens EDA is the new leader for Verification IP in the industry. This session will describe the protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter, Storage, 3DIC, Networking, Automotive, or Aerospace and Defense applications.

Today’s Semiconductors often target a manufacturing test coverage in excess of 99%. This target is particularly important for chips used in safety critical applications. However, there are usually a small number of faults that cannot be covered by structural testing. Functional Fault Grading provides a methodology to capture additional manufacturing test coverage without modifying the existing DFT architecture.

This session details how Siemens DFT centric verification technology tackles these challenges by providing a unified platform streamlined to Tessent flows, delivering industry leading performance and enhanced user experience, accelerating DFT verification closure while reducing cost and risk to reach DFT sign-off.

In this session, you will learn that Tessent deploys techniques to reduce simulation effort where possible.

In this session, you will be introduced to the Questa DFT Verification Platform, a comprehensive, high-productivity DFT verification solution.

In this session, you will learn Tessent's approach to Silicon Lifecycle Management (SLM).

In this session, you will learn five important aspects of why you should implement functional fault grading.

Welcome to Verification Academy Live.

Gone are the days when functional verification tools were solely measured by their performance metrics. The spotlight has shifted towards productivity in today's fast-paced development environment. In this session we explore how Siemens EDA prioritizes productivity and performance, enabling customers to optimize their verification cycles and swiftly uncover bugs. Discover the transformative impact of this paradigm shift on accelerating design validation and achieving faster time-to-market.

Learn how Siemens' and OneSpin have combined to deliver a best-in-class Static & Formal solution with a focus on addressing unsolved industry challenges. These solutions enable teams to achieve peak performance and deliver absolute hardware assurance.

Now that our acquisition of Avery Design Systems is complete, Siemens EDA is the new leader for Verification IP in the industry. This session will describe the protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter, Storage, 3DIC, Networking, Automotive, or Aerospace and Defense applications.

This session will cover Questa Verification IQ (VIQ), the next-generation, data-driven verification solution from Siemens EDA that transforms the verification process using collaboration, traceability, and analytics. VIQ enables greater collaboration among teams and utilizes machine learning and AI to boost verification productivity and efficiency.

Welcome to Verification Academy Live.

Gone are the days when functional verification tools were solely measured by their performance metrics. The spotlight has shifted towards productivity in today's fast-paced development environment. In this session we explore how Siemens EDA prioritizes productivity and performance, enabling customers to optimize their verification cycles and swiftly uncover bugs. Discover the transformative impact of this paradigm shift on accelerating design validation and achieving faster time-to-market.

Learn how Siemens' and OneSpin have combined to deliver a best-in-class Static & Formal solution with a focus on addressing unsolved industry challenges. These solutions enable teams to achieve peak performance and deliver absolute hardware assurance.

Now that our acquisition of Avery Design Systems is complete, Siemens EDA is the new leader for Verification IP in the industry. This session will describe the protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter, Storage, 3DIC, Networking, Automotive, or Aerospace and Defense applications.

This session will cover Questa Verification IQ (VIQ), the next-generation, data-driven verification solution from Siemens EDA that transforms the verification process using collaboration, traceability, and analytics. VIQ enables greater collaboration among teams and utilizes machine learning and AI to boost verification productivity and efficiency.

Welcome to Verification Academy Live.

Gone are the days when functional verification tools were solely measured by their performance metrics. The spotlight has shifted towards productivity in today's fast-paced development environment. In this session we explore how Siemens EDA prioritizes productivity and performance, enabling customers to optimize their verification cycles and swiftly uncover bugs. Discover the transformative impact of this paradigm shift on accelerating design validation and achieving faster time-to-market.

Learn how Siemens' and OneSpin have combined to deliver a best-in-class Static & Formal solution with a focus on addressing unsolved industry challenges. These solutions enable teams to achieve peak performance and deliver absolute hardware assurance.

In this session, you will learn how Tessent Embedded Analytics helps deal with the systemic complexity of large SoCs, providing intimate visibility of the real-world behavior of entire systems.

Now that our acquisition of Avery Design Systems is complete, Siemens EDA is the new leader for Verification IP in the industry. This session will describe the protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter, Storage, 3DIC, Networking, Automotive, or Aerospace and Defense applications.

This session will cover Questa Verification IQ (VIQ), the next-generation, data-driven verification solution from Siemens EDA that transforms the verification process using collaboration, traceability, and analytics. VIQ enables greater collaboration among teams and utilizes machine learning and AI to boost verification productivity and efficiency.

Welcome to Verification Academy Live.

Gone are the days when functional verification tools were solely measured by their performance metrics. The spotlight has shifted towards productivity in today's fast-paced development environment. In this session we explore how Siemens EDA prioritizes productivity and performance, enabling customers to optimize their verification cycles and swiftly uncover bugs. Discover the transformative impact of this paradigm shift on accelerating design validation and achieving faster time-to-market.

Learn how Siemens' and OneSpin have combined to deliver a best-in-class Static & Formal solution with a focus on addressing unsolved industry challenges. These solutions enable teams to achieve peak performance and deliver absolute hardware assurance.

In this session, you will learn how Tessent Embedded Analytics helps deal with the systemic complexity of large SoCs, providing intimate visibility of the real-world behavior of entire systems.

Now that our acquisition of Avery Design Systems is complete, Siemens EDA is the new leader for Verification IP in the industry. This session will describe the protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter, Storage, 3DIC, Networking, Automotive, or Aerospace and Defense applications.

This session will cover Questa Verification IQ (VIQ), the next-generation, data-driven verification solution from Siemens EDA that transforms the verification process using collaboration, traceability, and analytics. VIQ enables greater collaboration among teams and utilizes machine learning and AI to boost verification productivity and efficiency.

In this presentation, we will show how to automate the detection of hard-to-spot issues (e.g., CDC, FSM deadlock, combo loops, etc.) as early as possible in the design cycle with a continuous integration environment. In this flow, design quality is automatically checked at every code check-in and other scheduled intervals – which can reduce costs and drive predictable schedule execution.

Modern systems and products rely on complex microelectronic components now more than ever to monitor, control and process critical information. Due to their importance in the system or product, an exploit of these devices may result in a risk to personal safety, financial loss, exposure of personal information, and operation failure. Functional verification of microelectronic devices requires thorough methods and verifying that the ICs in the system are free of these exploits requires even more.

The Visualizer Debug Environment is the debug framework for simulation, static, formal, emulation, prototyping, analog and more. Visualizer and the Questa QIS technology ensures the fastest simulation while logging and prevents mismatches between regression simulations and debug simulations. Visualizer raises the debug abstraction using the Transaction viewer, the FSM view, the logic cone and the schematic viewer. Complex UVM testbench can be debugged easily in the wave window.

Big Data is transforming all industries, enabling them to innovate their products more rapidly and improve many aspects of our lives. EDA is powering these transformations. In this session, you will learn how Siemens’s latest offering, Questa Verification IQ (VIQ), can help you accelerate coverage closure, better manage your test and compute resources, and provide overall faster verification turnaround times by using analytics, collaboration, and traceability.

Testplans are a necessary step in the verification process but can be cumbersome depending on the user’s development environment. Available software may not be compatible with testplan plug-ins, and frustrating idiosyncrasies can arise during XML export. The YAML format is very similar to XML but is much more accessible and maintainable. This presentation discusses the benefits of using the YAML format as a base for testplan generation.

The use of Third-Party Intellectual Property (3PIP) in Aerospace and Defense (A&D) designs raises concerns about the level of trust that can be placed in 3PIP. In the absence of a full testbench with documentation what can be done to improve trust in 3PIP? Questa Formal AutoCheck provides an option for assessing designs with a low threshold for design comprehension. This presentation will explore the application of AutoFormal to 3PIP and provide examples of issues found in real 3PIP.

Discover how our cutting-edge Questa Simulation tools revolutionize the industry and deliver users' best product experience. During this session, we will unveil our latest product updates and discuss our exciting investments in the future of our product roadmap. Plus, you'll get a behind-the-scenes look at our strategic investments in the product, including our plans for expanding functionality, enhancing performance, and delivering even greater value to our users.

Designer focused tools are proven solutions that help you detect issues as early as possible in the design cycle; reducing costs, and driving predictable schedule execution. Using these solutions in a continuous integration environment -- where design quality is checked at every code check in and at other scheduled intervals -- product teams improve efficiency across the board. Additionally, this directly helps designers and the consumers other their IP by improving the quality of their code.

Siemens' OneSpin Trust and Security tools and apps have technologies built upon world-class formal engines, and provide quantitative data verification results desired in emerging cybersecurity standards. In this presentation we will introduce apps that provide an automated assessment platform, perform processor verification, and offer completeness checking to perform security verification in your IC.

You may have been told many different things about what AI/ML can do in the area of functional verification, but this presentation will give you the real story. Beginning with an overview of what AI/ML actually means and what is actually available today, we will share how we are incorporating this exciting technology across our product portfolio.

In this session anyone who is familiar with VHDL, Verilog, or SystemVerilog, and general verification practices, can learn the basics of formal. You will learn the basics of properties, how you can apply property checking to finding difficult corner case bugs, and easy-to-follow steps for verifying interfaces and other common design structures, as well as general design exploration.

Cloud's dramatic growth is driven by hopes for better throughput, easier workload management, and lower costs. However, you may be asking yourself, "Really? Can renting compute and data storage be a better value than my on-premises data center?” We will share some of our insights gained working with verification teams to scale projects to many 10's of thousands of simulations run on cloud.

In this presentation, we will show how to automate the detection of hard-to-spot issues (e.g., CDC, FSM deadlock, combo loops, etc.) as early as possible in the design cycle with a continuous integration environment. In this flow, design quality is automatically checked at every code check-in and other scheduled intervals – which can reduce costs and drive predictable schedule execution.

During this session we will unveil our latest Questa Simulation platform updates, with a behind-the-scenes look at our strategic investments in expanding functionality, enhancing performance, and delivering more intuitive debug capabilities.

Now that our acquisition of Avery Design Systems is complete, Siemens EDA is the industry leader for Verification IP. This session will describe the protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter, Storage, 3DIC, Networking, Automotive, or Aerospace and Defense applications.

This session will cover Verification IQ (VIQ), the next-generation, data-driven verification solution from Siemens EDA that transforms the verification process using analytics, collaboration, and traceability. VIQ utilizes machine learning to boost verification productivity, inspired by the collective feedback gathered from verification teams over many years.

This session discusses the Wilson Research Group Survey on ASIC and FPGA verification trends.

The key characteristics of the UVMF: accelerate environment development, reusable, scalable, and emulatable.

Formal verification uses mathematical and algorithmic methods to prove exhaustive results, requiring no testbench or stimulus.

This session will discuss writing constraints to characterize stimulus and configuration, creating prediction models, and defining coverage models with rapid testbench development utilizing the Questa Verification IP configurator to create high quality verification environments.

Modeling large integrated circuits for the workloads required for verification takes more computing than can be accomplished on CPU farms with 1000s of CPUs for many years.