Questa Design Solutions
Questa Design Solutions is an automated and integrated suite of verification tools for designers to improve initial RTL quality. Design Solutions analyzes code at the design stage to detect bugs early, to improve efficiency, enhance development predictability and ease pressure on schedules.
-
Wednesday, February 11th | 12:00 PM US/Pacific
Don’t Miss CDC Bugs in Low Power Designs!: Formal Meets Power Aware CDC
This webinar will discuss how Questa CDC Power Aware analysis can address this problem, as well as describe how Questa CDC combines exhaustive formal analysis with automated protocol assertions to prove safe crossings and filter functionally false positives.
-
Questa Design Solutions Sessions
-
Supercharge Your CDC & RDC Analysis with the Power of AI/ML
One of the biggest challenges in CDC/RDC verification is managing the complexity and time-consuming nature of identifying and resolving violations. CDC/RDC Assist addresses this challenge by leveraging AI/ML to automate and accelerate causality analysis. In this webinar, you will learn how to streamline CDC/RDC verification using machine learning to automate violation detection and resolution. -
Simulating CDC Reconvergence: Validating Robustness with Questa One Sim's Metastability Injection
This webinar will delve into Questa One Sim’s groundbreaking metastability injection capability, a pivotal advancement that brings the critical aspect of non-deterministic delay validation directly into the simulation realm. We will demonstrate how this new feature enables designers to actively model and inject varying metastability delays into synchronizer paths, allowing for rigorous verification of sequential reconvergence logic. -
Breaking Silos: Creating Synergistic Flows for Next-Gen Verification
In this webinar, through practical demonstrations and real-world examples, you'll see how next-generation verification goes beyond traditional approaches - enabling teams to break down silos, accelerate design cycles, and achieve higher quality results through intelligent automation and collaborative workflows. -
Questa RDC Assist: Accelerate Reset Closure with AI/ML
In this session, you will learn how RDC Assist helps users expedite their RDC Analysis and will discuss use models and best practices to utilize RDC Assist, and walk through a demo showing its power. -
New Advanced Techniques for Reset Domain Crossing (RDC) Analysis
In this session, you will learn new RDC, methodology, and automation techniques including; how to hierarchically characterize and structure reset (and clock) domain models for rapid analysis and re-use of IP-level RDC information as the design grows, waiver management flows, creating custom synchronizers and considerations for low power designs with UPF. -
Continuous Integration (CI) Driving Efficient Program Execution
In this session, you will learn the value of Continuous Integration during development and how Questa Design Solutions are ideally suited for implementation in CI flows. -
Questa Design Solutions as a Sleep Aid
In this session, you will gain an understanding about how Questa Design Solutions can help designers improve the quality of initial deliveries which drives more consistent schedule execution, and fewer late nights for the entire team. -
CDC and RDC Assist: Applying Machine Learning to Accelerate CDC Analysis
In this session, you will learn how the CDC and RDC Assist function of Questa CDC and Questa RDC use machine learning to accelerate setup, identification of design structures, and assist with constraint generation to help users achieve signoff more efficiently. -
Questa Lint vs Formal AutoCheck
In this session, you will gain an understanding of the similarities and differences between Lint and Formal AutoChecking tools, and how they can be used together to increase the quality of RTL deliverables. -
Fix an FPGA: Ways to Find and Fix FPGA Failures Faster
This session will identify how an RTL linting tool embedded within a continuous design checking process during code development and IP block integration can catch bug escapes earlier, while mitigating unforeseen FPGA development and design IP reuse cost. -
‘The Dog Ate my RTL’ Doesn’t Work Anymore
In this session, you will learn how to identify ways to remove the lack of a testbench as the cause of lower quality RTL and how to accomplish an improved RTL quality-focused flow. -
Introduction to Questa Lint and CDC for Designers
In this session, you will learn why code quality matters regardless of whether you are coding an ASIC, FPGA or IP block, what metastability is and how it will affect silicon bring-up and how addressing these points during the design process is critical to achieving tight schedules with limited resources. -
Acceleration Without Compromise: How to Finish Faster with Hierarchical CDC+RDC Methodologies
In this session, you will learn how to properly deploy hierarchical methodologies in CDC and RDC verification such that neither accuracy nor the performance expected from a hierarchical flow is compromised. -
CDC Philosophy: The Existential Questions of Constraints, Waivers, and Truth
In this session we will increase your confidence that the CDC results you see are truly reflective of the quality of your design. Using automated assertion-based verification flows and other verification techniques, the designer can know that the constraints and waivers applied are applied correctly. -
Improving Initial RTL Quality
This session will help you lower risks and improve team agility and development consistency by optimizing verification. Using designer-driven verification flows, designers get intent-focused insight to find issues when they are cheapest and easiest to fix. -
Questa AutoCheck: Advanced Linting
This session demonstrates the Questa AutoCheck advanced linting tool and how it can be used with Questa Lint and Questa X-Check for a full suite of RTL checks without a testbench. -
Preventing Glitch Nightmares on CDC Paths
As we are investing more in automotive and safety-critical designs, there is a renewed focus on design reliability. Glitches on clock-domain-crossing (CDC) signals will undoubtedly reduce reliability and lead to potential silicon failures. Hence, CDC verification is essential at both the RTL and the gate-level. Previously, we have been focusing on preventing and catching glitches on the data multiplexing paths. -
A Methodology for Comprehensive CDC+RDC Analysis
In this session, you will learn how to improve your comprehensive CDC and RDC methodology development schedules and predictability. -
Advance your Designs with Advances in CDC and RDC
In this session you will gain an understanding of valuable new capabilities available in Questa CDC, RDC and Signoff CDC. -
A Methodology for Comprehensive CDC Analysis
In this session we will talk about the right methodology of Clock-Domain Crossing analysis for early design closure. -
Reset-Domain Crossing Overview & Questa RDC Methodology
In this session, you will learn more about Reset-Domain Crossing problems and methods to address it. Then you will be introduced to the Questa RDC solution, how it catches true RDC issues and what is our proposed methodology of RDC flow to filter noise and have better QoR. -
When Are You Done Running CDC?
In this session you will learn whether or not you might still have asynchronous clock or reset issues lurking in your design, despite having identified the crossings, ensured synchronizers are present, and reviewed your code – or even already run CDC analysis, ensuring that all CDCs are solid. -
Why RDC Verification is an Emerging Requirement
In this session, you will learn what Reset-Domain Crossing (RDC) covers that Clock-Domain Crossing (CDC) does not and the appropriate time in the development cycle to deploy RDC. -
Gain a Design-to-Revenue Edge in FPGA & SoC Designs with a Full Deployment of CDC Analyses and Verification
This session explains the importance of a complete Clock-Domain Crossing (CDC) methodology to produce error-free silicon. -
What is CDC Protocol Verification: Why You Absolutely Need It to Prevent Bugs in Your Silicon
In this session, we discuss the pros and cons of various approaches to verifying Clock-Domain Crossing (CDC) protocols and we show how Questa CDC automatically generates protocol assertions. -
Accelerate Learning Curves and Achieve Program Goals Efficiently
In this session, you will learn how Questa Design Solutions accelerates development learning and improves and instruments development efficiency by providing design quality insight early, then monitoring throughout development.
-
-
Lint Forum Discussion
-
Block Container: Questa Design Solutions Introduction
-
Questa Design Solutions Overview
Questa Design Solutions tools are built on a consistent foundation with a common debug and user interface, producing designs that are correct-by-construction, proving designs meet the designer’s intent and the project’s quality requirements, and protecting the design throughout its development.
The high impact of design issues on projects
Mistakes happen, but finding and fixing issues late in programs increases overall program scope, as well as schedule and resource requirements. Competitive pressures push teams constantly to do more. Functional verification teams face significant challenges to build testbenches quickly, uncover design issues and enable rapid debug. Incomplete or incorrect bug fixes (or even a hurried introduction of new bugs) compound the problem. In addition, there are classes of design bugs that are challenging to catch at all in functional verification.
Superior capabilities and quality of results
Through a combination of data analysis, hierarchical and multi-modal technologies, leading analysis engines providing advanced static verification technologies, Questa Design Solutions provides fast analysis with high quality of results and minimal noise. These analyses provide not only results, but insight behind the issues, such as metrics, visualization and recommendations. Questa Design Solutions delivers these results and insights, without a testbench, with technologies built to scale across the most challenging designs and projects.
-