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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

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    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

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    • Featured Courses

      • Introduction to ISO 26262
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    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
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      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
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      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

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    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

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    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

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    • Coverage Cookbook

      • Introduction
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  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

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  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

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  • Static-Based Techniques

Static-Based Techniques

Static-Based Techniques

This topic focuses on static verification techniques such as Clock-Domain Crossing (CDC), Reset Domain Crossing (RDC), linting, as well as power-aware and gate-level domain crossing analyses.

CDC Verification Courses

Power Aware CDC Verification

Power Aware CDC Verification Course | Subject Matter Expert - Kurt Takara | Formal-Based Techniques Topic

In this course, you will learn the low power CDC methodology by discussing the low power CDC challenges, describing the UPF-related power logic structures relevant to CDC analysis, and explaining a low power CDC verification methodology.

Clock-Domain Crossing Verification

Clock-Domain Crossing Verification (CDC) Course | Subject Matter Expert - Harry Foster | Formal-Based Techniques Topic

This course introduces a set of steps for advancing an organization’s clock-domain crossing (CDC) verification skills, infrastructure, and metrics.

Featured On-Demand

Featured Recordings

Questa Design Solutions as a Sleep Aid

Questa Design Solutions as a Sleep Aid | Vinayak Desai - Subject Matter Expert

In this session, you will gain an understanding about how Questa Design Solutions can help designers improve the quality of initial deliveries which drives more consistent schedule execution, and fewer late nights for the entire team.

CDC and RDC Assist: Applying machine learning to accelerate CDC analysis

CDC and RDC Assist: Applying machine learning to accelerate CDC analysis | Atul Sharma - Subject Matter Expert

In this session, you will learn how the CDC and RDC Assist function of Questa CDC and Questa RDC use machine learning to accelerate setup, identification of design structures, and assist with constraint generation to help users achieve signoff more efficiently.

Questa Lint vs Formal AutoCheck

Questa Lint vs Formal AutoCheck Session | Kevin Campbell - Subject Matter Expert

In this session you will gain an understanding of the similarities and differences between Lint and Formal AutoChecking tools, and how they can be used together to increase the quality of RTL deliverables.

Fix an FPGA: Ways to Find and Fix FPGA Failures Faster

Fix an FPGA: Ways to Find and Fix FPGA Failures Faster | Subject Matter Expert - Buu Huynh | Siemens EDA Functional Verification Webinar Series

This session will identify how an RTL linting tool embedded within a continuous design checking process during code development and IP block integration can catch bug escapes earlier, while mitigating unforeseen FPGA development and design IP reuse cost.

Introduction to Questa Lint and CDC for Designers

Introduction to Questa Lint and CDC for Designers | Subject Matter Expert - Mathew Yee | Siemens EDA 2022 Functional Verification Webinar Series

In this session, you will learn why code quality matters regardless of whether you are coding an ASIC, FPGA or IP block, what metastability is and how it will affect silicon bring-up and how addressing these points during the design process is critical to achieving tight schedules with limited resources.

‘The Dog Ate my RTL’ Doesn’t Work Anymore

DAC 2021 | ‘The Dog Ate my RTL’ Doesn’t Work Anymore

In this session, you will learn how to identify ways to remove the lack of a testbench as the cause of lower quality RTL and how to accomplish an improved RTL quality-focused flow.

Improving Initial RTL Quality

Improving Initial RTL Quality Session | Subject Matter Expert - Chris Giles

This session will help you lower risks and improve team agility and development consistency by optimizing verification. Using designer-driven verification flows, designers get intent-focused insight to find issues when they are cheapest and easiest to fix.

Questa® Design Solutions Resources

Featured Static-Based Techniques Blog Posts

  • Non-stick surfaces and RTL design
  • Leave the House With a Clean Design
  • Significantly Improve Your FPGA Design Reliability by Using Custom CDC Synchronizers
  • No One Expects Gate Level CDC Verification and Glitch Detection for ASIC Signoff!
  • How to Avoid Metastability on Reset Signal Networks, a/k/a Reset Check is the New CDC
  • Are You Struggling to Reach Timing Closure with Your Low Power Design – You May Have CDC Problems!
  • Back to School: How to Educate Yourself and Your Colleagues About Formal and CDC Verification

Featured Static-Based Techniques Verification Horizons Articles

  • Don’t Forget the Protocol! A CDC Protocol Methodology to Avoid Bugs in Silicon
  • Comprehensive CDC Verification with Advanced Hierarchical Data Models
  • Reset Verification in SoC Designs
  • RTL CDC Is No Longer Enough — How Gate-Level CDC Is Now Essential to First Pass Success

Industry Static-Based Techniques Articles

  • Do You Know For Sure Your RISC-V RTL Doesn’t Contain Any Surprises?
  • Debug Solutions For Designers Accelerate Time To Verification
  • Out of the Verification Crisis: Improving RTL Quality
  • Northwest Logic Automates Verification of Clock Domain and Reset Domain Crossings Using Questa CDC and Questa RDC
  • Siemens Offers Insights into Gate Level CDC Analysis
  • An Integrated Approach To Power Domain And CDC Verification
  • How to achieve accurate reset domain crossing verification
  • First-Time FPGA Success Requires Exhaustive Examination of Clock-Domain Crossings
  • Crossed Wires On Domains
  • How Automated CDC Protocol Verification Accelerates Testing Processes
  • Automating the Pain Out of Clock-Domain Crossing Verification

Featured Static-Based Techniques White Papers

  • Scalable reset domain crossing (RDC) verification using hierarchical data models
  • Reset domain crossing for designs with set-reset flops
  • Systematic Methodology to Solve Reset Challenges in Automotive SoCs
  • Bringing reset and power domains together
  • Faster Reset Verification Closure with Intelligent Reset Domain Crossings Detection
  • Automating Clock-Domain Crossing Verification for DO-254 (and other Safety-Critical) Designs
  • Samsung: Clock-domain crossing aware sequential clock gating
  • Multi-mode clock-domain crossing verification enables analysis efficiency and accuracy
  • A CDC Protocol Methodology to Avoid Bugs in Silicon
  • Did power management break my CDC logic?
  • Out of the verification crisis
  • The Three Witches Preventing Glitch Nightmares on CDC Paths
  • A Specification-Driven Methodology for the Design and Verification of Reset Domain Crossing Logic
  • Clock-Domain Crossing Challenges in Latch Based Designs
  • Comprehensive CDC Verification Using Advanced Hierarchical Data Models
  • Systematic Speedup Techniques for Functional CDC Verification Closure
  • Power Aware CDC Verification of Dynamic Frequency And Voltage Scaling (DVFS) Artifacts
  • Accelerating CDC Verification Closure on Gate-Level Designs
  • Five Steps to Quality CDC Verification

Questa® Clock-Domain Crossing (CDC) Training

Learn about clock-domain crossing (CDC) design and verification and how to use Questa CDC to verify paths between asynchronous clock domains.

Featured Chapter:

  • Basic CDC Verification

Please visit the Functional Verification Library at Siemens EDA Learning Center to view more on-demand videos.

Featured Static-Based Techniques On-Demand Technical Sessions

  • Questa Design Solutions as a sleep aid
  • CDC and RDC Assist: Applying machine learning to accelerate CDC analysis
  • Questa Lint vs Formal AutoCheck
  • Fix an FPGA: Ways to Find and Fix FPGA Failures Faster
  • ‘The Dog Ate my RTL’ Doesn’t Work Anymore
  • Introduction to Questa Lint and CDC for Designers
  • Practical Flows for Continuous Integration: Making The Most of Your EDA Tools
  • Acceleration Without Compromise: How to Finish Faster with Hierarchical CDC+RDC
  • CDC Philosophy: The existential questions of constraints, waivers, and truth
  • Improving Initial RTL Quality
  • Trouble: Three CDC Glitches That Only a Netlist Will See
  • A Methodology for Comprehensive CDC+RDC Analysis
  • Advance your Designs with Advances in CDC and RDC
  • A Methodology for Comprehensive CDC Analysis
  • RDC Overview & Questa RDC Methodology
  • When Are You Done Running CDC?
  • Confronting Inevitability: Finding Clock and Reset Issues Before They Find You
  • Why Reset Domain Crossing Verification is an Emerging Requirement
  • Clock-Domain Crossing Analyses and Verification
  • Integrated Approach to Power Domain/Clock-Domain Crossing Checks
  • What Is CDC Protocol Verification, Prevent Bugs in Your Silicon
  • Questa CDC - Verifying CDC Reconvergence with Silicon-Accurate Models
  • Industrial-Strength Clock-Domain Crossing Verification

Featured Static-Based Techniques Seminar

  • CDC Technology Tips for Success

Seminar Sessions

  • Integrated Approach to Power Domain/Clock-Domain Crossing Checks
  • My Experience with Questa® CDC Bring-Up
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