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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

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    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

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    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

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    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

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    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

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    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

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  • Static-Based Techniques

Static-Based Techniques

Static-Based Techniques

This topic focuses on static verification techniques such as Clock-Domain Crossing (CDC), Reset Domain Crossing (RDC), linting, as well as power-aware and gate-level domain crossing analyses.

Featured On-Demand Recordings

Improving Initial RTL Quality

Improving Initial RTL Quality Session | Subject Matter Expert - Chris Giles

This session will help you lower risks and improve team agility and development consistency by optimizing verification. Using designer-driven verification flows, designers get intent-focused insight to find issues when they are cheapest and easiest to fix.

Trouble: Three CDC Glitches That Only a Netlist Will See

Trouble: Three CDC Glitches That Only a Netlist Will See | Subject Matter Expert - Ping Yeung | Siemens EDA 2021 Functional Verification Webinar Series

This session will help you lower risks, development schedules and costs by identifying netlist CDC issues that are never caught with normal RTL CDC runs

CDC Verification Courses

Power Aware CDC Verification

Power Aware CDC Verification Course | Subject Matter Expert - Kurt Takara | Formal-Based Techniques Topic

In this course, you will learn the low power CDC methodology by discussing the low power CDC challenges, describing the UPF-related power logic structures relevant to CDC analysis, and explaining a low power CDC verification methodology.

Clock-Domain Crossing Verification

Clock-Domain Crossing Verification (CDC) Course | Subject Matter Expert - Harry Foster | Formal-Based Techniques Topic

This course introduces a set of steps for advancing an organization’s clock-domain crossing (CDC) verification skills, infrastructure, and metrics.

Questa® Design Solutions Resources

  • Blog Posts
  • Articles
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Featured Static-Based Techniques Blog Posts

  • Leave the House With a Clean Design
  • Significantly Improve Your FPGA Design Reliability by Using Custom CDC Synchronizers
  • No One Expects Gate Level CDC Verification and Glitch Detection for ASIC Signoff!
  • How to Avoid Metastability on Reset Signal Networks, a/k/a Reset Check is the New CDC
  • Are You Struggling to Reach Timing Closure with Your Low Power Design – You May Have CDC Problems!
  • Back to School: How to Educate Yourself and Your Colleagues About Formal and CDC Verification

Featured Static-Based Techniques Verification Horizons Articles

  • Don’t Forget the Protocol! A CDC Protocol Methodology to Avoid Bugs in Silicon
  • Comprehensive CDC Verification with Advanced Hierarchical Data Models
  • Reset Verification in SoC Designs
  • RTL CDC Is No Longer Enough — How Gate-Level CDC Is Now Essential to First Pass Success

Industry Static-Based Techniques Articles

  • Out of the Verification Crisis: Improving RTL Quality
  • Northwest Logic Automates Verification of Clock Domain and Reset Domain Crossings Using Questa CDC and Questa RDC
  • Siemens Offers Insights into Gate Level CDC Analysis
  • An Integrated Approach To Power Domain And CDC Verification
  • How to achieve accurate reset domain crossing verification
  • First-Time FPGA Success Requires Exhaustive Examination of Clock-Domain Crossings
  • Crossed Wires On Domains
  • How Automated CDC Protocol Verification Accelerates Testing Processes
  • Automating the Pain Out of Clock-Domain Crossing Verification

Featured Static-Based Techniques White Papers

  • The Three Witches Preventing Glitch Nightmares on CDC Paths
  • A Specification-Driven Methodology for the Design and Verification of Reset Domain Crossing Logic
  • Clock-Domain Crossing Challenges in Latch Based Designs
  • Comprehensive CDC Verification Using Advanced Hierarchical Data Models
  • Systematic Speedup Techniques for Functional CDC Verification Closure
  • Power Aware CDC Verification of Dynamic Frequency And Voltage Scaling (DVFS) Artifacts
  • Accelerating CDC Verification Closure on Gate-Level Designs
  • Five Steps to Quality CDC Verification

Featured Static-Based Techniques Seminar

  • CDC Technology Tips for Success

Seminar Sessions

  • Integrated Approach to Power Domain/Clock-Domain Crossing Checks
  • My Experience with Questa® CDC Bring-Up

Featured Static-Based Techniques On-Demand Technical Sessions

  • Trouble: Three CDC Glitches That Only a Netlist Will See
  • A Methodology for Comprehensive CDC+RDC Analysis
  • Advance your Designs with Advances in CDC and RDC
  • A Methodology for Comprehensive CDC Analysis
  • RDC Overview & Questa RDC Methodology
  • When Are You Done Running CDC?
  • Confronting Inevitability: Finding Clock and Reset Issues Before They Find You
  • Why Reset Domain Crossing Verification is an Emerging Requirement
  • Clock-Domain Crossing Analyses and Verification
  • Integrated Approach to Power Domain/Clock-Domain Crossing Checks
  • What Is CDC Protocol Verification, Prevent Bugs in Your Silicon
  • Questa CDC - Verifying CDC Reconvergence with Silicon-Accurate Models
  • Industrial-Strength Clock-Domain Crossing Verification

Questa® Clock-Domain Crossing (CDC)

Learn about clock-domain crossing (CDC) design and verification and how to use Questa CDC to verify paths between asynchronous clock domains.

Featured Chapter:

  • Basic CDC Verification

Please visit the Functional Verification Library at Mentor Learning Center to view more on-demand videos.

Design Solutions Sessions

Questa® Lint Demo - Find and Fix RTL Issues

Questa Lint Demo Session | Subject Matter Expert - Tom Carlstedt-Duke

This session demonstrates how Questa Lint is used to find and fix RTL issues without a testbench or constraints

Questa® X-Check Demo - Identify "X" Issues

Questa X-Check Demo - Identify "X" Issues Session | Subject Matter Expert - Mark Eslinger

This session demonstrates how the Questa X-Check tool can identify X issues without any simulation, complementing Questa Lint and AutoCheck for a full suite of RTL checks.

Questa® AutoCheck Demo - Advanced Linting

Questa AutoCheck Demo - Advanced Linting Session | Subject Matter Expert - Mark Eslinger

This session demonstrates the Questa AutoCheck advanced linting tool and how it can be used with Questa Lint and Questa X-Check for a full suite of RTL checks without a testbench.

Questa® CDC Verification Demo

Questa CDC Verification Demo Session | Subject Matter Expert - Kurt Takara | Clock-Domain Crossing Verification (CDC) Course

This session demonstrates the Questa CDC Verification comprehensive solution to clock-domain verification.

Questa® Reset Domain Crossing (RDC) Demo

Questa® Reset Domain Crossing (RDC) Demo Session | Subject Matter Expert - Atul Sharma

This session will demonstrate the Questa RDC Verification Solution and will introduce key features in RDC GUI, like RDC Matrix, Directive Window and other debug features.

CDC Verification: Beyond Structural Analysis

CDC Verification: Beyond Structural Analysis | Automotive Functional Safety - Verification Forum 2021

In this session, we will cover the overall CDC methodology and cover CDC protocols and reconvergence in more details and show what could happen if these steps are skipped.

Trouble: Three CDC Glitches That Only a Netlist Will See

Trouble: Three CDC Glitches That Only a Netlist Will See | Subject Matter Expert - Ping Yeung | Siemens EDA 2021 Functional Verification Webinar Series

This session will help you lower risks, development schedules and costs by identifying netlist CDC issues that are never caught with normal RTL CDC runs

A Methodology for Comprehensive CDC+RDC Analysis

A Methodology for Comprehensive CDC+RDC Analysis | Subject Matter Expert - Kurt Takara | Siemens EDA 2021 Functional Verification Webinar Series

This session will help you improve your development schedules and predictability by identifying the key functions and processes that must be deployed in a comprehensive CDC and RDC methodology.

Handling Reset Domain Crossing for Designs with Set-Reset Flops

DVCon US 2021 | Handling Reset Domain Crossing for Designs with Set-Reset Flops

This paper specifically explores the different possible scenarios with such flops and problems introduced by these in the RDC closure. Which potentially can be dangerous and time consuming.

Preventing Glitch Nightmares on CDC Paths: The Three Witches

DVCon US 2021 | Preventing Glitch Nightmares on CDC Paths: The Three Witches

In this paper, we first explain the glitch problems in various types of CDC paths. Then, we summarize the automatic formal-based glitch detection methodology [2] that we have deployed for a few years.

Advance your Designs with Advances in CDC and RDC

Advance your Designs with Advances in CDC and RDC | Subject Matter Expert - Kurt Takara | Academy Live Web Seminar

In this session you will gain an understanding of valuable new capabilities available in Questa CDC, RDC and Signoff CDC that are important to leverage early and often in development to ensure working and error-free multi-clock and reset designs.

A Methodology for Comprehensive CDC Analysis

A Methodology for Comprehensive CDC Analysis | Subject Matter Expert - Atul Sharma | Academy Live Web Seminar

In this session we will talk about the right methodology of Clock-Domain Crossing analysis for early design closure.

RDC Overview & Questa RDC Methodology

RDC Overview & Questa RDC Methodology | Subject Matter Expert - Atul Sharma | Academy Live Web Seminar

In this session, you will learn more about Reset Domain Crossing problems and methods to address it. Then you will be introduced to the Questa-RDC solution, how it catches true RDC issues and what is our proposed methodology of RDC flow to filter noise and have better QoR.

When Are You Done Running CDC?

When Are You Done Running CDC? Session | Chris Giles - Subject Matter Expert

In this session you will learn whether or not you might still have asynchronous clock or reset issues lurking in your design, despite having identified the crossings, ensured synchronizers are present, and reviewed your code – or even already run CDC analysis, ensuring that all CDCs are solid.

Why Reset Domain Crossing Verification is an Emerging Requirement

Why Reset Domain Crossing Verification is an Emerging Requirement Session | Subject Matter Expert - Kurt Takara | Academy Live Web Seminar

In this session, you will learn what RDC covers that CDC does not and the appropriate time in the development cycle to deploy RDC.

Clock-Domain Crossing Analyses and Verification

Gain a Design-to-revenue Edge in FPGA and SoC Designs with a Full Deployment of Clock-Domain Crossing Analyses and Verification Session | Subject Matter Expert - Kurt Takara | Academy Live Web Seminar

This session explains the importance of a complete CDC methodology to produce error-free silicon.

Integrated Approach to Power Domain/Clock-Domain Crossing Checks

U2U Silicon Valley 2019 | Integrated Approach to Power Domain/Clock-Domain Crossing Checks

Power Aware/CDC simulations play an important role in System Resources block verification. The session discusses overcoming challenges in making the testbench work seamlessly across NON_PA and PA configurations.

No One Expects Gate Level CDC Verification and Glitch Detection for ASIC Signoff!

DAC 2018 | No One Expects Gate Level CDC Verification and Glitch Detection for ASIC Signoff!

In this session we will share a real world case study of how the customer applied Questa CDC the RTL level, then Questa Signoff CDC for gate-level CDC and glitch detection to wring out 3 glitches among millions of signals. (One of the glitch sources found was one that they had suspected; but the other two were a complete surprise.)

Clock-Domain Crossing with HDM - Enhanced Accuracy and Seamless Visibility at SOC Level

DAC 2018 | Clock-Domain Crossing with HDM - Enhanced Accuracy and Seamless Visibility at SOC level

CDC Analysis at SOC level involves huge challenges in terms of capacity, quality of results, and ease of debug, dependencies and ownership of IPs. The flagship SOC designs are typically the biggest and the most complex.

Why Gate Level CDC is Needed (Even After RTL CDC Closure!)

DAC 2017 | Why Gate Level CDC is Needed

In this session, you will learn how to leverage inputs from RTL CDC verification to automate and accelerate gate-level CDC verification closure with very "low noise" results.

My Experience with Questa® CDC Bring-Up

DVCon 2017 | My Experience with Questa® CDC Bring-Up

In this session, you will learn from Knowles Intelligent Audio on how they utilize Questa® CDC to achieve successful results.

What Is CDC Protocol Verification, Prevent Bugs in Your Silicon

What Is CDC Protocol Verification, and Why You Absolutely Need It To Prevent Bugs in Your Silicon Session | Subject Matter Expert - Kurt Takara | Academy Live Web Seminar

In this session, we discuss the pros and cons of various approaches to verifying CDC protocols and we show how Questa CDC automatically generates protocol assertions.

Orange is the New Black, Reset Verification is the New CDC

DAC 2016 | Orange is the New Black, Reset Verification is the New CDC

In this session we will show how to an automated formal app can exhaustively identify reset-specific killer bugs in your design.

Questa® CDC Power Aware Demo

Questa CDC Power Aware Demo Session | Subject Matter Expert - Kurt Takara | Power Aware CDC Verification Course

This session demonstrates the Questa® CDC Power Aware solution for verifying low power designs including clock domain crossing (CDC) and voltage domain crossing (VDC) paths.

How to Keep UPF from Ruining Your CDC Analysis

DAC 2015 | Formal Verification Wednesday | How to Keep UPF from Ruining Your CDC Analysis

In this session we will discuss the effects of advanced low power design on CDC by the addition of isolation cells, retention cells, level shifters, and dynamic voltage scaling.

Describing Low Power Logic with UPF

Describing Low Power Logic with UPF Session | Subject Matter Expert - Kurt Takara | Power Aware CDC Verification Course

This session describes the clock-domain crossing requirements for low power designs and explains the CDC issues introduced by power control logic.

Integrating Power Aware CDC into a Design Flow

Integrating Power Aware CDC into a Design Flow Session | Subject Matter Expert - Kurt Takara | Power Aware CDC Verification Course

This session describes a low power verification methodology and how the Questa® Power Aware CDC solution may be integrated into your design flow.

Understanding Low Power Impact on CDC Logic

Understanding Low Power Impact on CDC Logic Session | Subject Matter Expert - Kurt Takara | Power Aware CDC Verification Course

This session describes the impact of low power design techniques on design and CDC logic and also explains dynamic voltage and frequency scaling (DVFS) and its effect on CDC design and verification.

Power Aware CDC Introduction and Overview

Introduction and Overview Session | Subject Matter Expert - Kurt Takara | Power Aware CDC Verification Course

This session introduces the design challenges created by low power designs and the implications that these designs have on CDC verification.

Next-Generation Power Aware CDC Verification – What Have We Learned?

DVCon US 2015 Poster Paper - Next-Generation Power Aware CDC Verification – What Have We Learned?

This paper describes what we've learned from next-generation Power Aware CDC verification including low power design challenges.

Questa® CDC Demo

Questa CDC Session Video

Questa CDC addresses a number of critical verification issues that simply cannot be dealt with by simulation-based verification techniques.

Understanding Coverage Holes

Understanding Coverage Holes Session | Subject Matter Expert - Erich Marshner | Design & Verification in the SoC Era Seminar

This session will review the analysis of coverage results to identify and respond to coverage holes appropriately.

CDC Verification of an Accelerated Processing Unit

CDC Verification of an Accelerated Processing Unit Session | Subject Matter Expert - Tom Fitzpatrick | Advanced Verification Technologies in the Real World Seminar

This session will show how formal technology solutions ease the verification of critical elements of your designs such as Clock-Domain Crossings and CDC synchronization logic.

Introduction to CDC

Introduction to CDC Session | Subject Matter Expert - Harry Foster | Clock-Domain Crossing Verification (CDC) Course

This session introduces a survey of today’s CDC verification challenges, and the steps necessary to mature an organization’s CDC capabilities.

Metastability Verification Flow

Metastability Verification Flow Session | Subject Matter Expert - Harry Foster | Clock-Domain Crossing Verification (CDC) Course

This session introduces the three elements of a CDC verification flow, and discusses how to scale a CDC flow to a full chip solution.

Integrating CDC Into A Flow

Integrating CDC Into A Flow Session | Subject Matter Expert - Harry Foster | Clock-Domain Crossing Verification (CDC) Course

This session introduces a systematic set of steps to help you integrate Clock-Domain Crossing (CDC) into your flow.

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