Hello All,
I use the case statement at several locations in an FPGA project.
My interest is only in how the case statement gets synthesized. I suppose the SystemVerilog syntax governs the elaboration or linting process (the 1st stage of synthesis).
I need to know whether including either or both of these statements can improve (make smaller) the elaborated logic. More importantly I need to know which of them would be correct to use.
Assuming that the bus through which the case is fed has length N, the cases which I use do not cover all the logic permutations of length N. The cases are however mutually exclusive.
Let us call my cases: case_1, case_2, case_3.
1- What is the equivalent if-else-if logic for the following syntax:
(* full_case *)
case (sel_in)
case_1: begin
signal <= val_1;
end
case_2: begin
signal <= val_1;
end
case_3: begin
signal <= val_1;
end
endcase
2- What is the equivalent if-else-if logic for the following syntax:
(* parallel_case *)
case (sel_in)
case_1: begin
signal <= val_1;
end
case_2: begin
signal <= val_1;
end
case_3: begin
signal <= val_1;
end
endcase
3- Do the results change depending on whether “signal” in the examples above is a clocked or a combinational signal? or does using full_case or parallel_case become redundant perhaps?
Please note that I have already read ‘“full_case parallel_case“, the Evil Twins of Verilog Synthesis‘ and I have not found the answers to my questions spelled out there.
Thanks