I am trying to run my sequence_item class, one of the method(convert2string) in class is not printing as expected can any one help me to solve the issue.
package Definitions;
parameter DATAWIDTH = 32;
parameter ADDRWIDTH = 32;
parameter TRANS_WIDTH = 2;
parameter DATATRANFER_SIZE = 3;
parameter BURST_TYPE = 3;
//logic HSEL0, HSEL1, MUX_SEL; // Confusion for this line existance
//logic HRESETn, HCLK; // Confusion for this line existance
//------------------------------------- Parameters for memory module------------------------
parameter SLAVE_DATAWIDTH = 8;
parameter SLAVE_ADDRWIDTH = 8;
//---------------------------------------Tranfer types' enumeration------------------------------------------
typedef enum
{
IDLE = 'b00,
BUSY = 'b01,
NONSEQ = 'b10,
SEQ = 'b11
} Trans_t;
//--------------------------------------- Burst operation types enumeration----------------------------------
typedef enum
{
SINGLE = 'b000,
INCR = 'b001,
WRAP4 = 'b010,
INCR4 = 'b011,
WRAP8 = 'b100,
INCR8 = 'b101,
WRAP16 = 'b110,
INCR16 = 'b111
} BType_t;
//--------------------------------------- Burst Size (Bits) Enumeration---------------------------------------------
//---------------------------------------STRUCTURE for Address and Data--------------------------------------
//---------------------------------------Signal for Slave----------------------------------------------------
typedef enum
{
OKAY = 'b0,
ERROR = 'b1
} Response_t;
endpackage
import Definitions::*;
import uvm_pkg::*;
`include "uvm_macros.svh"
class transaction_a extends uvm_sequence_item;
rand logic [ADDRWIDTH-1:0] HADDR []; //this dynamic array is to store
rand logic [DATAWIDTH-1:0] HWDATA [];
rand bit HWRITE, HMASTLOCK, HREADY; //*
rand BType_t HBURST; //*
rand Trans_t HTRANS [];
logic [3:0] HPROT; //*
rand bit [2:0] HSIZE; //*
rand bit POSITION_BUSY []; //array to store position of busy
rand int NO_OF_BUSY_STATES; //Number of busy states in a transafer*
//Output data to DUT
logic [DATAWIDTH-1:0] HRDATA;
Response_t HRESP;
constraint size_of_ADDRandDATA {
solve HADDR before HWDATA;
HADDR.size == HWDATA.size;
}
constraint addnoteqz {
HADDR.size > 0;
}
constraint addrsize {
solve HBURST before HADDR;
if(HBURST == SINGLE)
HADDR.size == 1;
else if(HBURST inside {INCR4, WRAP4})
HADDR.size == 4;
else if(HBURST inside {INCR8, WRAP8})
HADDR.size == 8;
else if(HBURST inside {INCR16, WRAP16})
HADDR.size == 16;
else
HADDR.size == 5;
}
constraint addr_allignemnet {
if(HSIZE == 1)
foreach(HADDR[i])
HADDR[i][0] == '0;
else if(HSIZE == 2)
foreach(HADDR[i])
HADDR[i][1:0] == '0;
}
constraint addr_incr {
if(HBURST inside {INCR, INCR4, INCR8, INCR16})
foreach(HADDR[i])
if(i!=0)
HADDR[i] == HADDR[i-1] + (2**HSIZE);
}
constraint single_op {
if(HBURST inside {SINGLE})
{
HTRANS.size == 1;
HTRANS[0] inside {IDLE, NONSEQ};
}
}
constraint incr4816_wrap {
if(HBURST inside {INCR4, WRAP4, INCR8, WRAP8, INCR16, WRAP16})
HTRANS.size == HADDR.size;
foreach(HTRANS[i])
if(i!=0)
HTRANS[i] == SEQ;
else
HTRANS[i] ==NONSEQ;
}
constraint oincr {
if(HBURST inside {INCR})
HTRANS.size == HADDR.size;
foreach(HTRANS[i])
if(i == 0)
HTRANS[i] == NONSEQ;
else
HTRANS[i] inside {NONSEQ, SEQ};
}
constraint addrincr {
if(HBURST == INCR)
foreach(HTRANS[i])
if(i!=0)
if(HTRANS[i-1] == NONSEQ && HTRANS[i] == SEQ)
HADDR[i] == HADDR[i-1] + (2**HSIZE);
else if(HTRANS[i-1] == NONSEQ && HTRANS[i] == NONSEQ)
HADDR[i] != HADDR[i-1] + (2**HSIZE);
else if(HTRANS[i-1] == SEQ && HTRANS[i] == SEQ)
HADDR[i] == HADDR[i-1] + (2**HSIZE);
}
//////////////////////////////////////////////CONSTRAINTS/////////////////////////////////////////////////////////////////
`uvm_object_utils_begin(transaction_a)
`uvm_field_int(HWRITE, UVM_DEFAULT)
`uvm_field_int(HMASTLOCK, UVM_DEFAULT)
`uvm_field_int(HREADY, UVM_DEFAULT)
`uvm_field_int(HPROT, UVM_DEFAULT)
`uvm_field_int(HSIZE, UVM_DEFAULT)
`uvm_field_int(NO_OF_BUSY_STATES, UVM_DEFAULT)
`uvm_field_enum(BType_t, HBURST, UVM_DEFAULT)
`uvm_field_array_int(HADDR, UVM_DEFAULT)
`uvm_field_array_int(HWDATA, UVM_DEFAULT)
`uvm_field_array_int(POSITION_BUSY, UVM_DEFAULT)
`uvm_field_array_enum(Trans_t, HTRANS, UVM_DEFAULT)
`uvm_object_utils_end
virtual function string convert2string();
return $sformatf("[%0s] at time %t HADDR == %d, HWDATA == %d, HWRITE = %d, HMASTLOCK = %d, HREADY = %d, HBURST = %d, HTRANS = %d, HPROT = %d, HSIZE = %d, HRDATA= %d, HRESP =%d\n", get_type_name(), $time, this.HADDR, this.HWDATA, this.HWRITE, this.HMASTLOCK, this.HREADY, this.HBURST, this.HTRANS, this.HPROT, this.HSIZE, this.HRDATA, this.HRESP);
endfunction
function new(string name = "transaction_a");
super.new(name);
endfunction
endclass
module top;
transaction_a trans[5], trans2, trans3, trans4;
initial
begin
foreach(trans[i])
begin
trans[i] = transaction_a::type_id::create("trans[i]");
assert(trans[i].randomize);
//trans[i].convert2string();
end
trans[1].print();
trans[1].convert2string();
end
endmodule
output :
vlog -source -lint -sv sequence_item.sv -L C:/questasim64_2022.3/uvm-1.2/