Hello everyone,
I am a beginner in UVM. I have completed the UVM course offered by Cadence (“SystemVerilog Accelerated Verification using UVM”). So the course taught how to verify a synthetic routing module containing one input channel to send packets, one HBUS to configure the router and three output channel. So I learned how to create multiple UVCs, virtual sequencer, scoreboard with a reference model along with many other interesting concepts.
So I am now looking for applying these concepts to test new designs possibly with something similar setup where I will need to create multiple UVCs. So far I am having a hard time finding something useful as I will also need the HDL code for the design as well.
Can you anyone give me some ideas/links? Thanks in advance.
I agree. There is so much content online in terms of projects, step-by-step, classes, tutorials, etc about Software development. There is hardly anything regarding System Verilog/UVM verification.
We are just told to read the spec, learn this one example of a Testbench for DFF or a MUX and off you go, time to verify a hyperthreading CPU with a coherent memory.
There is no easy way to have a real-world SV/UVM environment at home. edaplayground is just that, a playground. I have been asking around if there are some projects that are looking for volunteer help in developing a Testbench or verifying a design. Somehow there is a ton of open-source projects to volunteer for in the Software side of things.
I wish I knew how to help you. I put my 2c here just in case someone gives a constructive feedback, so I can get notified as well.
There are many available resources. You just need to look at appropriate places (and ask in forums such as here, though this is MENT/Siemens sponsored/hosted). Start with GitHub. A large scale, industry level SoC with opensource RTL & DV (UVM, SVA, Lint etc.) is at opentitan.org
Good luck
Hi , you can try to verify some designs available at below site. You might need to start from scratch, but our YAPP project and cadence lecture manual will help a lot
https://opencores.org/projects