Memory Read showing xxx values for APB verification

SystemVerilog
1

I have a read task that reads from a memory using apb protocol but prdata signal shows unknown values … where am i wrong??
Here is the EDA playground link for full code: APB_Slave_inprogress - EDA Playground

//Read task
task Read;
begin
for (int j = 0; j< 64; j= j+1) begin
@(negedge pclk) begin
psel = 1;
penb =1;
pwrite = 0;
paddr = j;
@(posedge pclk);
#1 rdata = prdata;
$display("PADDR %h, PRDATA %h ",paddr,rdata);
end
end
end
endtask

2

In reply to criz:

Several subtle issues I see in your TB code. A quick fixed version (not fully tested) is below.

  1. You are using (mis?) begin/end unnecessarily. Especially with SV, task/functions do not need begin…end itself. You’ve begin…end even around @(negedge clk) begin → this means a block of code blocked by this timing event. Most likely it is unintended.
  2. paddr width changes from TB to DUT - why? A lint would flag it easily.
  3. Fix indentation, please

Good luck


  task Write;
 begin
   @(negedge pclk);// begin 
	 	psel = 1;
       	penb = 0;
    @(negedge pclk);
     for (int i = 0; i < 5; i=i+1) begin
       @(negedge pclk);// begin 
        penb = 1 ;
	 	pwrite = 1;
		paddr = i;
		pwdata = i;
      $display("%0t PADDR %h, PWDATA %h  ",$time, paddr,pwdata);
	 //end
//end
   end
 end
endtask
3

In reply to criz:

Hi,
I found few issues that you can verify.

  1. your TB uses 8b paddr, but in dut, you use 32b, that creates the issue that you can never write anything.
  2. for apb, it needs to do setup-> access → setup → access(look at your apb_st). So you can not write 2 data back to back w/o going back to setup. Your dut is doing the right thing, but your TB is not. So the end result is that you did not successfully write in consecutive address, you only write to addr 2/4/6/8…, so when you try to read the location that is not written, you will see x. Hope this helps.