Memory Read showing xxx values for APB verification

SystemVerilog
2

In reply to criz:

Several subtle issues I see in your TB code. A quick fixed version (not fully tested) is below.

  1. You are using (mis?) begin/end unnecessarily. Especially with SV, task/functions do not need begin…end itself. You’ve begin…end even around @(negedge clk) begin → this means a block of code blocked by this timing event. Most likely it is unintended.
  2. paddr width changes from TB to DUT - why? A lint would flag it easily.
  3. Fix indentation, please

Good luck


  task Write;
 begin
   @(negedge pclk);// begin 
	 	psel = 1;
       	penb = 0;
    @(negedge pclk);
     for (int i = 0; i < 5; i=i+1) begin
       @(negedge pclk);// begin 
        penb = 1 ;
	 	pwrite = 1;
		paddr = i;
		pwdata = i;
      $display("%0t PADDR %h, PWDATA %h  ",$time, paddr,pwdata);
	 //end
//end
   end
 end
endtask