This is a general question about Agent and Monitor build_phase.
While building and connecting a UVM verification environment, I am seeing a very odd problem. In the Agent, if I do not create the monitor twice then I will get an error during the build_phase:
# ** Fatal: (SIGSEGV) Bad handle or reference.
Without the second create command for the monitor, the build_phase for the Monitor will not show up in the logs.
Are there any methods I can use to more thoroughly debug this problem?
Create command for monitor in agent:
my_mon = my_monitor::type_id::create(“my_mon”, this);
Log file with one create command for the monitor:
UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_phase.svh(1124) @ 0: reporter [PH/TRC/STRT] Phase ‘common’ (id=27) Starting phase
UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_phase.svh(1381) @ 0: reporter [PH/TRC/DONE] Phase ‘common’ (id=27) Completed phase
UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_phase.svh(1403) @ 0: reporter [PH/TRC/SCHEDULED] Phase ‘common.build’ (id=45) Scheduled from phase common
UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_phase.svh(1124) @ 0: reporter [PH/TRC/STRT] Phase ‘common.build’ (id=45) Starting phase
UVM_INFO /home/agent/my_agent.sv(47) @ 0: uvm_test_top.my_env_i.my_agent_i [DEBUG] MY AGENT Starting my_agent build_phase
UVM_INFO /home/agent/my_agent.sv(71) @ 0: uvm_test_top.my_env_i.my_agent_i [DEBUG] MY AGENT Starting my_agent build_phase complete
UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_phase.svh(1499) @ 0: reporter [PH/TRC/WAIT_PRED_OF_SUCC] Phase ‘common.build’ (id=45) *** No pred to succ other than myself, so ending phase***
UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_phase.svh(1356) @ 0: reporter [PH_END] Phase ‘common.build’ (id=45) ENDING PHASE
UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_phase.svh(1381) @ 0: reporter [PH/TRC/DONE] Phase ‘common.build’ (id=45) Completed phase
UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_phase.svh(1403) @ 0: reporter [PH/TRC/SCHEDULED] Phase ‘common.connect’ (id=57) Scheduled from phase common.build
UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_phase.svh(1124) @ 0: reporter [PH/TRC/STRT] Phase ‘common.connect’ (id=57) Starting phase
Log file with two create commands for the monitor:
UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_phase.svh(1124) @ 0: reporter [PH/TRC/STRT] Phase ‘common’ (id=27) Starting phase
UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_phase.svh(1381) @ 0: reporter [PH/TRC/DONE] Phase ‘common’ (id=27) Completed phase
UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_phase.svh(1403) @ 0: reporter [PH/TRC/SCHEDULED] Phase ‘common.build’ (id=45) Scheduled from phase common
UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_phase.svh(1124) @ 0: reporter [PH/TRC/STRT] Phase ‘common.build’ (id=45) Starting phase
UVM_INFO /home/agent/my_agent.sv(47) @ 0: uvm_test_top.my_env_i.my_agent_i [DEBUG] MY AGENT Starting my_agent build_phase
UVM_INFO /home/agent/my_agent.sv(72) @ 0: uvm_test_top.my_env_i.my_agent_i [DEBUG] MY AGENT Starting my_agent build_phase complete
UVM_INFO /home/agent/my_monitor.sv(48) @ 0: uvm_test_top.my_env_i.my_agent_i.my_mon [DEBUG] MY MONITOR my_monitor build_phase started
UVM_INFO /home/agent/my_monitor.sv(64) @ 0: uvm_test_top.my_env_i.my_agent_i.my_mon [DEBUG] MY MONITOR my_monitor build_phase complete
UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_phase.svh(1499) @ 0: reporter [PH/TRC/WAIT_PRED_OF_SUCC] Phase ‘common.build’ (id=45) *** No pred to succ other than myself, so ending phase***
UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_phase.svh(1356) @ 0: reporter [PH_END] Phase ‘common.build’ (id=45) ENDING PHASE
UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_phase.svh(1381) @ 0: reporter [PH/TRC/DONE] Phase ‘common.build’ (id=45) Completed phase
UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_phase.svh(1403) @ 0: reporter [PH/TRC/SCHEDULED] Phase ‘common.connect’ (id=57) Scheduled from phase common.build
UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_phase.svh(1124) @ 0: reporter [PH/TRC/STRT] Phase ‘common.connect’ (id=57) Starting phase
UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_phase.svh(1499) @ 0: reporter [PH/TRC/WAIT_PRED_OF_SUCC] Phase ‘common.connect’ (id=57) *** No pred to succ other than myself, so ending phase***
UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_phase.svh(1356) @ 0: reporter [PH_END] Phase ‘common.connect’ (id=57) ENDING PHASE
UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_phase.svh(1381) @ 0: reporter [PH/TRC/DONE] Phase ‘common.connect’ (id=57) Completed phase
UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_phase.svh(1403) @ 0: reporter [PH/TRC/SCHEDULED] Phase ‘common.end_of_elaboration’ (id=69) Scheduled from phase common.connect
UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_phase.svh(1124) @ 0: reporter [PH/TRC/STRT] Phase ‘common.end_of_elaboration’ (id=69) Starting phase
You will likely need to post code which demonstrates your issues, as it is difficult to debug something without knowing what you are doing.
Do you need to call create() twice in a row? Or is there other code in between calls that may clear your handle? Is there code in your environment which alters the agent behavior?
Yes, I needed to call create() twice. In all of the UVM projects I have worked on, I’ve never had to do this before, and it is limited to the monitor.
Once I get more time, I will post code to this thread. For now, I wanted to reach out to the community and see if anyone has experienced this before.
I was able to resolve the issue the created the odd build_phase problem. There was a missing “;” in the code on the line preceding the create() command for the monitor. It was only after a routine code inspection that the missing “;” was found.
Another tool used to find the problem was the testbench topology. Without the second create() command, the monitor was not seen in topology report. A good linting tool would also help.
The most disturbing problem is the compiler did not flag this is an error and was the simulation was allowed to proceed forward.
Hopefully this information will be helpful to any community developers who experience the same problem.