Search Results
Filters
Advanced Search
2056 Results
-
Generating SystemVerilog Assertion (SVA) Properties with Property Assist
Webinar - Jul 16, 2025 by Mark Eslinger
In this webinar, you will learn how Questa Property Assist automatically generates SystemVerilog Assertions (SVA) that describe the behavior of hardware designs, using AI technology. In addition, Property Assist turns user prompts into optimized LLM prompts, retrieves LLM provided solutions, and presents the best generated SVA solutions for the user.
-
Accelerating Functional Coverage with Questa One CX
Webinar - Jun 18, 2025 by Chris Crile
This webinar introduces Questa One Sim CX, an innovative coverage-driven simulation solution that revolutionizes SystemVerilog UVM verification workflows.
-
Accelerating Functional Coverage with Questa One CX
Resource (Slides (.PDF)) - Jun 18, 2025 by Chris Crile
In this webinar, you learn the benefits of using Questa One Sim CX in your constrained random verification environment.
-
Industrial-Grade AI in EDA: From Promise to Practice — A Siemens Panel at DAC 2025
Resource (Verification Horizons Blog) - Jun 17, 2025 by Harry Foster
The AI revolution is reshaping everything from entertainment to enterprise software — but what does it take to bring artificial intelligence into the high-stakes, precision-driven world of electronic design automation (EDA)? That’s the central question behind a standout DAC 2025 panel hosted by Siemens EDA: “ Achieving Industrial-Grade AI in EDA: Challenges, Lessons, and Opportunities .”
-
Generative AI: The Hype, The Hope, The Hard Truths — And the Debate at DAC
Resource (Verification Horizons Blog) - Jun 17, 2025 by Harry Foster
The semiconductor industry is no stranger to bold claims. But few topics today spark more debate — or more genuine uncertainty — than generative AI. At DAC 2025, we’re bringing this debate directly to the Pavilion stage with a dynamic panel.
-
Accelerated Safety Assurance with Questa One Functional Safety Solution
Resource (Verification Horizons Blog) - Jun 16, 2025 by Jake Wiltgen
In an increasingly digital world, the safety and reliability of electronic systems are no longer optional, they are essential. Whether we’re talking about the circuitry in modern cars, life-saving medical devices, or complex industrial automation systems, the need for robust functional safety methodologies is greater than ever.
-
Tackling Emerging DFT Verification Challenges with Questa One
Webinar - Jun 12, 2025 by Jake Wiltgen
In this webinar, you will learn how the Questa One DFT Verification solution, combined with Tessent Silicon Lifecycle Solutions delivers an evolution in user experience and performance to address these emerging verification challenges.
-
Tackling Emerging DFT Verification Challenges with Questa One
Resource (Slides (.PDF)) - Jun 12, 2025 by Jake Wiltgen
In this webinar, you learn about the latest DFT-aware Questa One methodologies and engines tailored to Tessent workflows.
-
Enhancing Automotive Safety Verification Using Questa One Sim FX
Resource (Slides (.PDF)) - Jun 04, 2025 by Ann Keffer
In this webinar, you will learn how Questa One Sim FX optimizes fault campaigns through advanced features including fault list optimization and test ranking capabilities.
-
Enhancing Automotive Safety Verification Using Questa One Sim FX
Webinar - Jun 04, 2025 by Ann Keffer
In this webinar, you will learn how Questa One Sim FX optimizes fault campaigns through advanced features including fault list optimization and test ranking capabilities. The webinar will demonstrate the tool's seamless integration with existing testbench environments (UVM and native), eliminating the need for extensive modifications and reducing setup overhead.
-
From Rule-Based Beginnings to AI-Driven Design: Tracing the Evolution of AI in EDA
Resource (Verification Horizons Blog) - Jun 03, 2025 by Harry Foster
As we gear up for the 62nd Design Automation Conference (DAC) in San Francisco, one of the most anticipated events is the Accellera-sponsored luncheon panel : Can AI Cut Costs in Electronic Design & Verification While Accelerating Time-To-Market? This panel brings together voices from across the industry to examine how artificial intelligence is reshaping the design and verification landscape.
-
Questa One Avery VIP: Accelerated Confidence in Complex Protocol Verification
Resource (Paper (.PDF)) - Jun 03, 2025 by Gordon Allan
This paper describes specific verification challenges, showcases innovative solutions for real-world stimulus and hardware/software co-simulation, and highlights the value delivered to early adopters.
-
Questa One Avery VIP: Accelerated Confidence in Complex Protocol Verification
Paper - Jun 03, 2025 by Gordon Allan
Questa One Avery VIP’s cutting-edge technologies promise to enhance productivity and ease of use in the rapidly expanding landscape of complex interfaces and memory protocols, spanning SoC designs, 3D IC chiplets, and FW/SW integration. This paper describes specific verification challenges, showcases innovative solutions for real-world stimulus and hardware/software co-simulation, and highlights the value delivered to early adopters.
-
Redefining Static and Formal Verification
Paper - May 29, 2025 by Chris Giles
Recent studies show that first-time silicon success is at an all-time low. It is therefore fair to question whether verification technologies and methodologies deliver the solutions that teams require. Simultaneously, new technologies such as AI yield exciting new opportunities to redefine verification methodologies. Siemens EDA delivers a transformative use of static and formal technologies, empowered by AI and new forms of automation.
-
Redefining Static and Formal Verification
Resource (Paper (.PDF)) - May 29, 2025 by Chris Giles
Siemens EDA delivers a transformative use of static and formal technologies, empowered by AI and new forms of automation. This provides much-needed new verification solutions that improve total user productivity by enabling faster engineers, delivering faster engines and optimizing development by requiring fewer workloads.
-
A Guide to UPF-based Power Intent Verification with Questa One
Paper - May 29, 2025 by Chandu Challapalli
This white paper takes a close look at the verification side of UPF with Questa One Sim Power Aware. The focus here is on how to confirm that the described power intent is correctly wired up, tested and functionally sound throughout the design flow. We’ll look at multiple verification approaches and review the tools and technologies offered by Questa One that help design teams close the loop on low-power verification.
-
A Guide to UPF-based Power Intent Verification with Questa One
Resource (Paper (.PDF)) - May 29, 2025 by Chandu Challapalli
This white paper takes a close look at the verification side of UPF with Questa™ One Sim Power Aware. The focus here is on how to confirm that the described power intent is correctly wired up, tested and functionally sound throughout the design flow.
-
DFT Verification: Tackling the Evolving Challenges
Resource (Verification Horizons Blog) - May 29, 2025 by Jake Wiltgen
Technological advancement continues as a blistering pace, and the demand for highly reliable systems is paramount across various industries. Safety critical systems and high-performance and heterogenous compute are just a sampling of end markets where customers require the utmost reliability.
-
Streamlining Requirements Traceability using Questa Verification IQ Testplan Author
Resource (Slides (.PDF)) - May 28, 2025 by Nishtha
In this webinar, you will learn how verification engineers can visualize complex requirement relationships at a glance, identify and address coverage gaps in real-time, and ensure comprehensive requirement implementation and testing.
-
Streamlining Requirements Traceability using Questa Verification IQ Testplan Author
Webinar - May 28, 2025 by Nishtha
In this webinar, discover how Questa Verification IQ Testplan Author seamlessly integrates with Application Lifecycle Management tools (such as Siemens Polarion and Jama Connect) to deliver a powerful, collaborative traceability solution that transforms your verification workflow.
-
Solving the Semiconductor Verification Crisis: From Problem to Productivity
Resource (Slides (.PDF)) - May 21, 2025 by Harry Foster
In this webinar, you will discover how a connected, data-driven, and AI-enhanced approach transforms verification into a proactive, scalable system built for 3D ICs, chiplets, and software-defined architectures—delivering higher quality, faster results, and greater productivity across your engineering team.
-
Solving the Semiconductor Verification Crisis: From Problem to Productivity
Webinar - May 21, 2025 by Harry Foster
The semiconductor industry is facing Verification Productivity Gap 2.0 —a crisis driven by mounting design complexity, growing security demands, and workforce shortages. Traditional verification methods alone can’t keep up. This webinar explores the latest industry trends and challenges shaping functional verification, then introduces Questa One —Siemens’ smart verification platform engineered to meet these demands head-on.
-
Enhanced Simulation Debugging through Advanced Capabilities of Visualizer
Conference - May 20, 2025 by Satish Banukumar
In this session, you will learn what was holding our Questa Classic users back from adopting Visualizer as their debugger, even though we are sold on the advanced capabilities and performance gains, our strategy to overcome this, and then close out the talk with Visualizer features that have worked well and improvements we hope to see.
-
Enhanced Simulation Debugging through Advanced Capabilities of Visualizer
Resource (Slides (.PDF)) - May 20, 2025 by Satish Banukumar
This session will start with the introduction of our DUT – the advanced robotic system -- and the corresponding design and verification challenges of constantly reuse code resulting from rapid growth in the last decade.
-
Functional Verification Using Siemens Questa Simulation Technologies
Resource (Slides (.PDF)) - May 20, 2025 by Nirmala Balakrishnan
In this session, you will learn how Tsavorite Scalable Intelligence harnessed the UVM Framework to automate testbench and make-file infrastructure generation and got them started quickly with QuestaSim regressions.