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• Epilogue: 2022 Study Summary and Key Findings

  Resource (Verification Horizons Blog) - Jan 23, 2023 by Harry Foster

  This is the last in a sequence of blogs that presents the findings from our new 2022 Wilson Research Group Functional Verification Study. I opened this blog series with a  Prologue posting that provided an overview of this year’s study. I think it is only fitting that I end this series with an Epilogue posting that summarizes some of this year’s key findings.

• Conclusion: Deeper Dive into Non-Trivial Bug Escapes

  Resource (Verification Horizons Blog) - Jan 15, 2023 by Harry Foster

  Our study results show that the IC/ASIC market has matured its verification processes overtime to address growing complexity, predominately driving by the emergence of SoC-class designs in the mid-2000 timeframe. Today we find the FPGA market is maturing its verification processes.

• Part 12: IC/ASIC Verification Results Trends

  Resource (Verification Horizons Blog) - Jan 09, 2023 by Harry Foster

  A metric often track to measure efficiency is ASIC project completion compared to the original schedule, as shown in Figure 12-1. Here we found that 66 percent of IC/ASIC projects were behind schedule, while 27% of projects were behind schedule by 27 percent.

• Part 11: ASIC/IC Low Power Trends

  Resource (Verification Horizons Blog) - Jan 02, 2023 by Harry Foster

  As shown in figure 11-1, we found that 72% of design projects actively manage power. In fact, we found that the larger the design, the greater the concern for power management. Obviously, a wide variety of techniques, ranging from simple clock-gating to complex hypervisor/OS-controlled power management schemes are employed whose requirements require verification.

• Part 10: IC/ASIC Language and Library Adoption Trends

  Resource (Verification Horizons Blog) - Dec 26, 2022 by Harry Foster

  In this blog I plan to discuss various IC/ASIC language and library adoption trends. Figure 10-1 shows the aggregated adoption trends for languages used to create RTL designs across all market segments and all regions of the world. We see continual interest in SystemVerilog for RTL creation.

• Part 8: IC/ASIC Resource Trends

  Resource (Verification Horizons Blog) - Dec 18, 2022 by Harry Foster

  In this blog, I plan to discuss the growing IC/ASIC project resource trends resulting from growing design complexity. Figure 8-1 shows the percentage of total IC/ASIC project time spent in verification. You can see two extremes in this graph. In general, projects that spend very little time in verification are typically working on designs with a good deal of existing pre-verified design IP, which is integrated to create a new product.

• Part 9: ASIC Verification Technology Adoption Trends

  Resource (Verification Horizons Blog) - Dec 18, 2022 by Harry Foster

  The ASIC market in the mid-2000 timeframe underwent growing pains to address increased verification complexity, predominately brought on with the adoption of SoC-class designs. This maturing of ASIC projects’ processes is clearly visible when comparing various simulation-based verification technology adoption trends from 2007 through 2022 as shown in Figure 9-1, although the overall dynamic verification technique adoption trends have remained flat for the past few studies.

• Harry Foster - Siemens EDA

  Resource (Interview) - Dec 08, 2022 by Harry Foster

  Interview with Harry Foster of Siemens EDA about the surprising results from the 2022 Wilson Research Study and Osmosis' presentations.

• The state of functional verification: Crisis or opportunity?

  Resource (Recording) - Dec 08, 2022 by Harry Foster

• Part 7: IC/ASIC Design Trends

  Resource (Verification Horizons Blog) - Nov 28, 2022 by Harry Foster

  Now my plan is to shift the focus in this series of blogs from FPGA trends to IC/ASIC trends. And specifically in this blog, I present trends related to various aspects of design to illustrate growing design complexity. Fig. 7-1 shows the trends from the 2012 through the 2022 studies in terms of active IC/ASIC design project by design sizes (gates of logic and datapath, excluding memories).

• Part 6: FPGA Language and Library Trends

  Resource (Verification Horizons Blog) - Nov 21, 2022 by Harry Foster

  In this blog, I’ll present FPGA design and verification language adoption trends. It is not uncommon for FPGA projects to use multiple languages when constructing their RTL and testbenches. This practice is often due to legacy code as well as purchased IP. Hence, you might note that the percentage adoption for some of the languages that I present sums to more than one hundred percent.

• Functional Verification Study - 2022

  Webinar - Nov 16, 2022 by Harry Foster

  In this session, Harry Foster highlights the key findings from the 2022 Wilson Research Group Functional Verification Study, and provides his interpretation and analysis behind today's emerging trends.

• Part 5: FPGA Verification Technology Adoption Trends

  Resource (Verification Horizons Blog) - Nov 13, 2022 by Harry Foster

  In this blog I present verification techniques and technologies adoption trends, as identified by the 2020 Wilson Research Group study. An interesting trend we see in the FPGA space is a continual maturing of its functional verification processes. In fact, we find that the FPGA design space is about where the ASIC/IC design space was about seven years ago in terms of pre-lab verification maturity—and it is catching up quickly. A question you might ask is, “What is driving this trend?”

• Part 4: FPGA Verification Effort Trends (Continued)

  Resource (Verification Horizons Blog) - Nov 06, 2022 by Harry Foster

  In this blog I continue the discussion of FPGA verification effort trends by looking at where engineers spend their time. Verification engineers are not the only project stakeholders involved in the verification process. Design engineers spend a significant amount of their time in verification too, as shown in fig. 4-1. In 2022, design engineers spent on average 58 percent of their time involved in design activities and 42 percent of their time in verification.

• Part 3: FPGA Verification Effort Trends

  Resource (Verification Horizons Blog) - Oct 30, 2022 by Harry Foster

  In this blog I focus on FPGA verification effort trends. Directly asking study participants how much effort they spend in verification will not work. The reason is that it’s hard to find a paper or article on verification that doesn’t start with the phrase: “Seventy percent of a project’s effort is spent in verification…” In other words, the industry is already biased to respond with this effort value. Yet, there are really no creditable references to quantify this value.

• Industry Data and Surveys

  Track - Oct 24, 2022 by Harry Foster

  Every two years, Siemens EDA commissions Wilson Research Group to conduct a broad, vendor-independent survey of design verification practices around the world. Results of the functional verification study demonstrate an ongoing convergence of design and verification practices toward a common methodology.

• Part 1: The Global FPGA Semiconductor Market

  Resource (Verification Horizons Blog) - Oct 16, 2022 by Harry Foster

  In this blog, I present trends related to various aspects of FPGA design to illustrate growing design complexity. The 2021 global semiconductor market was valued at $552.5 billion after experiencing a 24 percent growth over 2020. The FPGA portion of the semiconductor market was valued at about $5.3 billion in 2021. The FPGA semiconductor market is expected to reach a value of $9.3 billion by 2030, growing at a compounded annual growth rate (CAGR) of 6.5 percent during this forecast period.

• IC/ASIC Functional Verification Trend Report - 2020

  Resource (Technical Paper) - Oct 22, 2021 by

• Mil/Aero Analysis Functional Verification Study - 2020

  Resource (Technical Paper) - Jan 20, 2021 by Harry Foster

• Functional Verification Study - 2020

  Session - Oct 13, 2020 by Harry Foster

  In this session, Harry Foster highlights the key findings from the 2020 Wilson Research Group Functional Verification Study, and provides his interpretation and analysis behind today's emerging trends.

• FPGA Verification Challenges and Opportunities

  Article - Nov 28, 2018 by Harry Foster

  There have been multiple studies on IC/ASIC functional verification trends published over the years. [1][2][3][4] However, there are no published studies specifically focused on Field-Programmable Gate Array (FPGA) verification trends.

• Functional Verification Study - 2018

  Session - Oct 15, 2018 by Harry Foster

  In this session, Harry Foster highlights the key findings from the 2018 Wilson Research Group Functional Verification Study, and provides his interpretation and analysis behind today's emerging trends.

• Functional Verification Study - 2016

  Session - Oct 14, 2016 by Harry Foster

  In this session, Harry Foster highlights the key findings from the 2016 Wilson Research Group Functional Verification Study, and provides his interpretation and analysis behind today's emerging trends.

• FPGA Trends in Functional Verification - 2014

  Session - May 08, 2015 by Harry Foster

  Harry Foster discusses the FPGA verification trends from the 2014 Wilson Research Group Functional Verification Study, and provides some insight into its findings.

• ASIC/IC Trends in Functional Verification - 2014

  Session - May 08, 2015 by Harry Foster

  Harry Foster discusses the IC/ASIC verification trends from the 2014 Wilson Research Group Functional Verification Study, and provides some insight into its findings.