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Hardware Emulation: Three Decades of Evolution

Article - Mar 11, 2015 Dr. Lauro Rizzatti - Rizzatti LLC

About 30 years ago, when computers revolutionized the semiconductor design process, a new verification technology appeared on the horizon under the name of hardware emulation. It was implemented in a big-box and billed as being able to verify and debug chip designs.
Evolving the Use of Formal Model Checking in SoC Design Verification

Article - Mar 11, 2015 Ram Narayan

Project RAPID is a hardware-software co-design initiative in Oracle Labs that uses a heterogeneous hardware architecture combined with architecture-conscious software to improve the energy efficiency of database-processing systems.
Small, Maintainable Tests

Article - Mar 11, 2015 Ashley Winn - Sondrel IC Design Services

In any verification environment it takes a significant amount of work to keep all the tests running and to ensure that each test continues to be effective. To make this job easier, tests need to be kept as short as possible and should be written at the highest level of abstraction possible for the feature being tested.
Functional Coverage Development Tips: Do’s and Don'ts

Article - Mar 11, 2015 Samrat Patel, Vipul Patel - eInfochips

The fundamental goal of a verification engineer is to ensure that the Device Under Test (DUT) behaves correctly in its verification environment. As chip designs grow larger and more complex with thousands of possible states and transitions, a comprehensive verification environment must be created that minimizes development effort.
UVM Connect 2.3.0 Kit

Resource (Tarball) - Mar 10, 2015 John Stickley
UVM Connect 2.3.0 Primer

Resource (Reference Documentation) - Mar 10, 2015 John Stickley
Coverage Data Exchange is No Robbery…Or is It?

Resource (Paper (.PDF)) - Mar 03, 2015 Darron May

Coverage is extremely important to the modern verification flow. Most vendors have already figured that unifying data across all verification engines leads to a more efficient and integrated environment. There are many challenges to be solved unifying and sharing data across a single vendor’s tool set which are further complicated when wanting to share data across multiple vendors’ tool sets.
Coverage Data Exchange is No Robbery…Or is It?

Resource (Poster Paper) - Mar 03, 2015 Darron May

In this poster paper, presented at DVCon 2015, you learn more that the Unified Coverage Database was architected in 2005 to unify coverage collection across all verification engines, UCDB was first released within Questa and ModelSim in early 2006 as a way of natively storing, analyzing and reporting on functional coverage, code coverage and assertions.
Coverage Data Exchange is No Robbery…Or is It?

Paper - Mar 03, 2015 Darron May

Over the last few years all the major vendors have realized that unifying the way coverage is stored in a common database allows the results of multiple verification tools to be combined and for these tools to share the data to improve coverage closure. Simulation, Emulation and Formal engines should all be using the same database to provide the user with the complete picture, and allow the analysis of all data in a common way.
Boosting Regression Throughput by Reusing Setup Phase Simulation

Resource (Paper (.PDF)) - Mar 03, 2015 Rohit Jain

This paper will discuss different types of designs (Verilog, VHDL, System Verilog) and use case scenarios (long running setup phases), that are suitable for this checkpoint and restore methodology.
Boosting Regression Throughput by Reusing Setup Phase Simulation

Paper - Mar 03, 2015 Rohit Jain

This paper will discuss how to write the design so that the common initial setup phase simulation is done once and then used as a foundation to run different tests later on, including the ability to change test stimulus to simulate different test behaviors. We will also discuss what type of designs (Verilog, VHDL, SystemVerilog, UVM-based, SystemC, C/C++ models, PLI/FLI/VPI etc.) will fit in this methodology and what a designer can do to make his design fit for such methodology.
Are You Smarter Than Your Testbench? With a Little Work You Can Be

Paper - Mar 03, 2015 Rich Edelman

As design size increases complexity, testbenches complexity grows at least as fast. Today's testbench is as complicated as the design itself, and care must be taken to understand it from both a performance and functionality point of view. This paper will discuss ways to keep check on the testbench performance and to understand the functionality being implemented and the effectiveness of the tests.
Are You Smarter Than Your Testbench? With a Little Work You Can Be

Resource (Paper (.PDF)) - Mar 03, 2015 Rich Edelman

This paper will discuss ways to keep check on the testbench performance and to understand the functionality being implemented and the effectiveness of the tests.
UVM Sans UVM: An Approach to Automating UVM Testbench Writing

Resource (Paper (.PDF)) - Mar 02, 2015 Rich Edelman

This paper is targeted towards a verification team without any UVM background, and it describes a simple template and generator, without any extra time overhead, and without any extra budget overhead.
UVM Sans UVM: An Approach to Automating UVM Testbench Writing

Paper - Mar 02, 2015 Rich Edelman

The SystemVerilog 1 UVM 2 promises to improve verification productivity while enabling teams to share tests and testbenches between projects and divisions. This promise can be achieved; the UVM is a powerful methodology for using constrained randomization to reach higher functional coverage goals and to explore combinations of tests without having to write each one individually. Unfortunately, the UVM promise can be hard to reach without training, practice and some significant expertise.
UVM Connect 2.3 Kit

Resource (Tarball) - Feb 18, 2015 John Stickley
Part 1: FPGA Design Trends

Resource (Verification Horizons Blog) - Feb 08, 2015 Harry Foster

In my previous blog, I introduced the 2014 Wilson Research Group Functional Verification Study ( click here ). The objective of my previous blog was to provide an overview on our large, worldwide industry study. The key findings from this study will be presented in a set of upcoming blogs. In this blog, I present trends related to various aspects of FPGA design to illustrate growing design complexity.
Prologue: The 2014 Wilson Research Group Functional Verification Study

Resource (Verification Horizons Blog) - Jan 21, 2015 Harry Foster

This is the first in a series of blogs that presents the findings from our new 2014 Wilson Research Group Functional Verification Study. However, unlike my previous Wilson Research Group functional verification study blogs ( click here ), which focused on the IC/ASIC market, I plan to begin this set of blogs with an exclusive focus on FPGA trends.
Understanding and Minimizing Study Bias (2014 Study)

Resource (Verification Horizons Blog) - Jan 21, 2015 Harry Foster

This blog is a continuation of a series of blogs that present the highlights from the 2014 Wilson Research Group Functional Verification Study (for a background on the study, click here ). In this blog I discuss the issue of study bias, and what we did to address these concerns.
Coverage Cookbook - Japanese Release

Resource (Cookbook Japanese Translation) - Jan 14, 2015
Introduction to Questa X-Check

Webinar - Dec 20, 2014 Doug Smith

In this session, you will learn how Questa X-Check finds sources of X in your design and identifies issues where X is propagated and corrupts properly initialized registers.
Power Aware Verification in Mixed-Signal Simulation

Resource (Paper (.PDF)) - Dec 10, 2014

Power efficiency is a very important metric in designing mobile and other industrial SoCs. Various power saving techniques are used to reduce power consumption. To verify the power distribution network and power state transitions in SoC designs, power-aware verification is performed with the power architecture described in UPF. Many of those SoCs are mixed-signal in nature and have power-regulation functionality on the chip.
Introduction to Questa CDC

Webinar - Nov 12, 2014 Doug Smith

In this session, you will learn how the Questa Clock-Domain Crossing (CDC) solution focuses on the interaction between these clock-domains.
Integrate Ethernet QVIP in a Few Hours: an A-to-Z Guide

Article - Nov 01, 2014 Prashant Dixit

Functional verification is critical in the development of today's complex digital designs. Increasing hardware complexity generally tracks Moore's Law; however, verification complexity grows at an even faster rate. Verification cycle is widely acknowledged as the major bottleneck in design methodology. Up to 70 percent of design time and resources are spent on functional verification. And yet, functional bugs are the number one cause of silicon re-spins.
Fast Track to Productivity Using Questa Verification IP

Article - Nov 01, 2014 Dave Aerne

This article demonstrates these features while referencing the PCIe and AXI4 Questa VIP components.