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UVM Rapid Adoption: A Practical Subset of UVM

Conference - Mar 31, 2015 Tom Fitzpatrick

This session focusses on defining a subset of the UVM base classes, methods, and macros that will enable engineers to learn UVM more quickly and become productive with using UVM for the verification of most types and sizes of digital designs modeled in VHDL, Verilog or SystemVerilog. You might be surprised at just how small of a subset of UVM is really needed in order to verify complex designs effectively with UVM.
UVMC 2.3.0 Library

Resource (Reference Documentation) - Mar 15, 2015

v2.3.0 The UVM Connect library provides TLM1 and TLM2 connectivity between SystemC and SystemVerilog models and components. It also provides a UVM Command API for accessing and controlling UVM simulation from SystemC (or C or C++). This document provides a user guide to the UVM-Connect API package itself as well as a primer on TLM-2.0 usage in general.
Samsung: Clock-Domain Crossing Aware Sequential Clock Gating

Resource (Paper (.PDF)) - Mar 15, 2015 Jianfeng Liu, Mi-Suk Hong, Kyungtae Do, Jung Yun Choi, Jaehong Park S. LSI, Samsung Electronics Co. Ltd.

In this paper, you learn the need for handling CDCs as part of sequential clock gating. A new approach was presented where CDCs were natively modeled as a cost function in the power optimization objective.
Samsung: Clock-Domain Crossing Aware Sequential Clock Gating

Paper - Mar 15, 2015 Jianfeng Liu, Mi-Suk Hong, Kyungtae Do, Jung Yun Choi, Jaehong Park S. LSI, Samsung Electronics Co. Ltd.

In this paper, we present an algorithm to handle CDC violations as part of the objective function for sequential clock gating optimizations. With the proposed algorithm, we have obtained an average of 22% sequential power savings – this is within 3% of the power savings obtained by the CDC unaware sequential clock gating. In comparison, the state-of-the-art two-pass solution is leading to an almost complete loss of power savings.
Part 2: FPGA Verification Effort Trends

Resource (Verification Horizons Blog) - Mar 11, 2015 Harry Foster

This blog is a continuation of a series of blogs related to the 2014 Wilson Research Group Functional Verification Study ( click here ). In my previous blog , I focused on FPGA design trends. In this blog, I present findings from our study related to the effort spent in verification. Directly asking study participants how much effort they spend in verification will not work.
Does Design Size Influence First Silicon Success?

Article - Mar 11, 2015 Harry Foster

In 2002 and 2004, Collett International Research, Inc. conducted its well-known ASIC/IC functional verification studies, which provided invaluable insight into the state of the electronic industry and its trends in design and verification at that point in time. However, after the 2004 study, no additional Collett studies were conducted, which left a void in identifying industry trends.
Successive Refinement: A Methodology for Incremental Specification of Power Intent

Article - Mar 11, 2015 Adnan Khan, John Biggs & Eamonn Quigley - Arm

In this article, we present the UPF Successive Refinement methodology in detail. We explain how power management constraints can be specified for IP blocks to ensure correct usage in a power-managed system. We explain how a system’s power management architecture can be specified in a technology-independent manner and verified abstractly, before implementation. We also explain how implementation information can be added later.
Power Aware RTL Verification of USB 3.0 IPs

Article - Mar 11, 2015 Gayathri SN, Badrinath Ramachandra - L&T Technology Services Limited

This article describes a specific Power Management scheme used in a USB 3.0 Device IP controller. It also describes how Questa Power Aware helped IP designers realize reliable, accurate and scalable low power architectures and comprehensive verification of these architectures. Additionally, this also shares the experience in using the UPF to define various power domains, isolation strategies and methods to control power states from the testbench.
Hardware Emulation: Three Decades of Evolution

Article - Mar 11, 2015 Dr. Lauro Rizzatti - Rizzatti LLC

About 30 years ago, when computers revolutionized the semiconductor design process, a new verification technology appeared on the horizon under the name of hardware emulation. It was implemented in a big-box and billed as being able to verify and debug chip designs.
Evolving the Use of Formal Model Checking in SoC Design Verification

Article - Mar 11, 2015 Ram Narayan

Project RAPID is a hardware-software co-design initiative in Oracle Labs that uses a heterogeneous hardware architecture combined with architecture-conscious software to improve the energy efficiency of database-processing systems.
Small, Maintainable Tests

Article - Mar 11, 2015 Ashley Winn - Sondrel IC Design Services

In any verification environment it takes a significant amount of work to keep all the tests running and to ensure that each test continues to be effective. To make this job easier, tests need to be kept as short as possible and should be written at the highest level of abstraction possible for the feature being tested.
Functional Coverage Development Tips: Do’s and Don'ts

Article - Mar 11, 2015 Samrat Patel, Vipul Patel - eInfochips

The fundamental goal of a verification engineer is to ensure that the Device Under Test (DUT) behaves correctly in its verification environment. As chip designs grow larger and more complex with thousands of possible states and transitions, a comprehensive verification environment must be created that minimizes development effort.
UVM Connect 2.3.0 Kit

Resource (Tarball) - Mar 10, 2015 John Stickley
UVM Connect 2.3.0 Primer

Resource (Reference Documentation) - Mar 10, 2015 John Stickley
Coverage Data Exchange is No Robbery…Or is It?

Resource (Paper (.PDF)) - Mar 03, 2015 Darron May

Coverage is extremely important to the modern verification flow. Most vendors have already figured that unifying data across all verification engines leads to a more efficient and integrated environment. There are many challenges to be solved unifying and sharing data across a single vendor’s tool set which are further complicated when wanting to share data across multiple vendors’ tool sets.
Coverage Data Exchange is No Robbery…Or is It?

Resource (Poster Paper) - Mar 03, 2015 Darron May

In this poster paper, presented at DVCon 2015, you learn more that the Unified Coverage Database was architected in 2005 to unify coverage collection across all verification engines, UCDB was first released within Questa and ModelSim in early 2006 as a way of natively storing, analyzing and reporting on functional coverage, code coverage and assertions.
Coverage Data Exchange is No Robbery…Or is It?

Paper - Mar 03, 2015 Darron May

Over the last few years all the major vendors have realized that unifying the way coverage is stored in a common database allows the results of multiple verification tools to be combined and for these tools to share the data to improve coverage closure. Simulation, Emulation and Formal engines should all be using the same database to provide the user with the complete picture, and allow the analysis of all data in a common way.
Boosting Regression Throughput by Reusing Setup Phase Simulation

Resource (Paper (.PDF)) - Mar 03, 2015 Rohit Jain

This paper will discuss different types of designs (Verilog, VHDL, System Verilog) and use case scenarios (long running setup phases), that are suitable for this checkpoint and restore methodology.
Boosting Regression Throughput by Reusing Setup Phase Simulation

Paper - Mar 03, 2015 Rohit Jain

This paper will discuss how to write the design so that the common initial setup phase simulation is done once and then used as a foundation to run different tests later on, including the ability to change test stimulus to simulate different test behaviors. We will also discuss what type of designs (Verilog, VHDL, SystemVerilog, UVM-based, SystemC, C/C++ models, PLI/FLI/VPI etc.) will fit in this methodology and what a designer can do to make his design fit for such methodology.
Are You Smarter Than Your Testbench? With a Little Work You Can Be

Paper - Mar 03, 2015 Rich Edelman

As design size increases complexity, testbenches complexity grows at least as fast. Today's testbench is as complicated as the design itself, and care must be taken to understand it from both a performance and functionality point of view. This paper will discuss ways to keep check on the testbench performance and to understand the functionality being implemented and the effectiveness of the tests.
Are You Smarter Than Your Testbench? With a Little Work You Can Be

Resource (Paper (.PDF)) - Mar 03, 2015 Rich Edelman

This paper will discuss ways to keep check on the testbench performance and to understand the functionality being implemented and the effectiveness of the tests.
UVM Sans UVM: An Approach to Automating UVM Testbench Writing

Resource (Paper (.PDF)) - Mar 02, 2015 Rich Edelman

This paper is targeted towards a verification team without any UVM background, and it describes a simple template and generator, without any extra time overhead, and without any extra budget overhead.
UVM Sans UVM: An Approach to Automating UVM Testbench Writing

Paper - Mar 02, 2015 Rich Edelman

The SystemVerilog 1 UVM 2 promises to improve verification productivity while enabling teams to share tests and testbenches between projects and divisions. This promise can be achieved; the UVM is a powerful methodology for using constrained randomization to reach higher functional coverage goals and to explore combinations of tests without having to write each one individually. Unfortunately, the UVM promise can be hard to reach without training, practice and some significant expertise.
UVM Connect 2.3 Kit

Resource (Tarball) - Feb 18, 2015 John Stickley
Part 1: FPGA Design Trends

Resource (Verification Horizons Blog) - Feb 08, 2015 Harry Foster

In my previous blog, I introduced the 2014 Wilson Research Group Functional Verification Study ( click here ). The objective of my previous blog was to provide an overview on our large, worldwide industry study. The key findings from this study will be presented in a set of upcoming blogs. In this blog, I present trends related to various aspects of FPGA design to illustrate growing design complexity.