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2302 Results

  • A New Approach to Low Power Verification: Power Aware Apps

    The effective verification of low power designs has been a challenge for many years now. The IEEE Std 1801-2015 Unified Power Format (UPF) standard for modeling low power objects and concepts is continuously evolving to address the low power challenges of today’s complex designs.

  • Simplifying Mixed-Signal Verification

    Mixed-signal design is the art of taking real world analog information, such as light, touch, sound, vibration, pressure, or temperature, and bringing it into the digital world for processing.

  • Understanding and Minimizing Study Bias (2018 Study)

    This blog is a continuation of a sequence of blogs that present the highlights from the 2018 Wilson Research Group Functional Verification Study (for a background on the study, ( click here ). This blog, which discusses the issue of study bias and what we did to address these concerns, is basically a repeat of this topic from my 2014 and 2016 blog series. However, there are a few observations related specifically to our 2018 study worth mentioning.

  • Prologue: The 2018 Wilson Research Group Functional Verification Study

    This is the first in a sequence of blogs that presents the findings from our new 2018 Wilson Research Group Functional Verification Study. Similar to my previous 2016 Wilson Research Group functional verification study blogs, I plan to begin this sequence of blogs with an exclusive focus on FPGA trends.

  • Functional Verification Study - 2018

    In this session, Harry Foster highlights the key findings from the 2018 Wilson Research Group Functional Verification Study, and provides his interpretation and analysis behind today's emerging trends.

  • Planning for DO-254

    In this session, we will discuss what is involved in planning phase for DO-254 . It is intended to give the view insight on the planning artifacts and their content.

  • Planning for DO-254

    In this session, we will discuss what is involved in planning phase for DO-254. It is intended to give the view insight on the planning artifacts and their content.

  • DO-254 in Simple Terms

    In this session, you will be introduced to DO-254 from a designer’s perspective in layman’s terms and will be gain a fundamental understanding of what DO-254 is and its applications.

  • DO-254 in Simple Terms

    In this session, you will be introduced to DO-254 from a designer’s perspective in layman’s terms and will be gain a fundamental understanding of what DO-254 is and its applications.

  • Introduction to DO-254

    The purpose of this track is to provide engineers or technical leads with basic understanding of DO-254 key concepts. DO-254 has been around for over 15 years and has been applied almost exclusively in the commercial Aerospace industry. Because it has been focused on a subset of the electronic hardware market, many engineers and companies have little to no knowledge of DO-254.

  • UVM 1800.2 and the New & Improved Cookbook

  • A Fresh Look at Creating a UVM Environment - UVM Framework

  • A Fresh Look at Creating a UVM Environment - All Slides

  • A Fresh Look at Creating a UVM Environment - Introduction

  • Vista Virtual Prototyping

  • Visualizer Debug Introduction

  • UVM 1800.2 & The New and Improved UVM Cookbook

  • UVM 1800.2 & The New and Improved UVM Cookbook

    This session will start with an overview of the changes in UVM 1800.2 from UVM 1.2 and 1.1d so you can be prepared to embrace the new Standard.

  • UVM-2017 v0.9 Library Code for IEEE 1800.2

  • UVM 2017-1.0 Reference Implementation

  • UPF Information Model: The Future of Low-Power Verification Today

    The IEEE 1801-2015 or UPF 3.0 language reference manual (LRM) introduces a new conceptual low power verification methodology, known as ‘UPF information model’. The model captures power management information from UPF commands and their semantics applied on designs (generally specified in different HDL e.g. Verilog, SystemVerilog, VHDL etc.). The UPF commands are power intents applied on a design, intended to leverage low power.

  • UPF Information Model: The Future of Low-Power Verification Today

    The IEEE 1801-2015 or UPF 3.0 language reference manual (LRM) introduces a new conceptual low power verification methodology, known as ‘UPF information model’. The model captures power management information from UPF commands and their semantics applied on designs (generally specified in different HDL e.g. Verilog, SystemVerilog, VHDL etc.). The UPF commands are power intents applied on a design, intended to leverage low power.

  • Using Automation to Close the Loop Between Functional Requirements and Their Verification

    This session will define a “Verified by” relationship between the Verification Requirement and the Coverage Intent work item and the Verification Requirement and Test work item. The final pieces needed to close the loop is the proof that the coverage item was met in a passing simulation.

  • Using Automation to Close the Loop Between Functional Requirements and their Verification

    This session will define a “Verified by” relationship between the Verification Requirement and the Coverage Intent work item and the Verification Requirement and Test work item.

  • Power Aware Simplifies Parametric PA-SIM Regression