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ISO 26262: Simple Terms

Session - Apr 21, 2020 Jake Wiltgen

This session takes a broad look at ISO 26262, the safety standard for electronic and electronic systems deployed into automobiles. In this session, we will review the activities and work products expected within the majority of chapters defined in ISO 26262.
ISO 26262 in Simple Terms

Resource (Slides (.PDF)) - Apr 21, 2020 Jacob Wiltgen
ISO 26262 Requirements Management

Resource (Slides (.PDF)) - Apr 21, 2020 Jacob Wiltgen
Introduction to ISO 26262

Track - Apr 20, 2020 Jake Wiltgen

The purpose of this track is to provide engineers and managers with a basic understanding of the key concepts of ISO 26262. This includes information on the scope of the standard, how the standard addresses the broader automotive supply chain, and key requirements defined at each phase of the product lifecycle.
Deadlock Verification for Dummies: The Easy Way Using SVA and Formal

Resource (Paper (.PDF)) - Apr 15, 2020 Mark Eslinger

The risk of a design going into deadlock is not something you can effectively verify with simulation. You could try to do it with traditional formal liveness and safety properties, but that can be a painful and error prone process.
Deadlock Verification for Dummies: The Easy Way Using SVA and Formal

Paper - Apr 15, 2020 Mark Eslinger

RTL simulation cannot directly tell if a digital system is deadlocked. This paper shares new formal automation technology that leverages industry- standard SystemVerilog Assertion code to specify constraints and properties that detect deadlock in RTL designs, while leveraging linear-temporal logic, computational-tree logic, liveness and safety analyses under-the-hood.
UVM Coding Guidelines: Tips & Tricks You Probably Didn’t Know

Webinar - Apr 10, 2020 Chris Spear

In this session, you will learn how to create testbench transactions and component classes that are easily debugged and reused. Additional rules are shown for SystemVerilog code to prevent common bugs.
Code Generation Merging

Resource (Slides (.PDF)) - Apr 01, 2020 Jonathan Craft

In this session, you will learn about UVMF code generation capabilities that allow you to quickly produce new iterations of generated code that automatically transfer previous manual edits from earlier versions.
Code Generation Merging

Session - Apr 01, 2020 Jonathan Craft

In this session, you will learn about UVMF code generation capabilities that allow you to quickly produce new iterations of generated code that automatically transfer previous manual edits from earlier versions.
Mind the GAP(s): Closing and Creating GAPS Between Design and Verification

Resource (Slides (.PDF)) - Mar 31, 2020 Chris Giles

This workshop will examine several gaps in development processes that can result in verification escapes, and suggest solutions that can prevent bugs from finding their way into customer deployments.
Mind the Gap(s): Closing and Creating Gaps Between Design and Verification

Webinar - Mar 31, 2020 Chris Giles

This session will examine several gaps in development processes that can result in verification escapes, and suggest solutions that can prevent bugs from finding their way into customer deployments.
FPGA Verification Maturity: A Quantitative Analysis

Webinar - Mar 26, 2020 Harry Foster

While multiple studies on IC/ASIC functional verification trends have been published, there have been no studies specifically focused on FPGA verification trends. To address this dearth of information, Harry presents the results from a recent large industry study on functional verification.
FPGA Verification Maturity: A Quantitative Analysis

Resource (Slides (.PDF)) - Mar 26, 2020
If You Don’t Know, Now You Know: Terminal Boundary Dictates Power Aware Macros

Resource (Paper (.PDF)) - Mar 14, 2020 Progyna Khondkar

This paper identifies and resolves the fundamental problems of integrating, hardening and verifying soft and hard macros in larger systems with a power aware DVIF perspective.
If You Don’t Know, Now You Know: Terminal Boundary Dictates Power Aware Macros

Paper - Mar 14, 2020 Progyna Khondkar

This paper distinctively studies the inherent integration features of soft and hard macros that are inevitable or low power designs today. This has been done by thoroughly identifying the semantic gaps between physical interpretations of macros with their low power orientations. With real design examples, we provided simple and manageable macro verification solutions that are portable, comply with UPF 3.1 standards and re-usable in consecutive projects.
Verify Thy Verifyer

Article - Mar 01, 2020 Srinivasan Venkataramanan, Ajeetha Kumari - VerifWorks

Design Verification is a field that requires a lot of thinking and equally a lot of coding. Tighter time-to-market adds a lot of schedule pressure to the teams coding those testbenches and test cases. The advent of UVM (Universal Verification Methodology) as the standard framework, has helped the industry make good progress in terms of structured testbenches. One of the primary objectives of UVM is to build robust, reusable testbenches.
Using Questa SLEC to Speed Up Verification of Multiple HDL Outputs

Article - Mar 01, 2020 Tomáš Vaňák - Codasip

Questa SLEC, the formal analysis app from Siemens EDA, was designed to automatically compare a block of code ("specification" RTL) with its functional equivalent that has been slightly modified ("implementation" RTL), helping design teams save considerable amounts of time and resources. Codasip, the leading provider of configurable RISC-V® IP, has come up with a new use of this tool: the verification team uses it to compare a fully UVM-verified HDL code.
AI-Based Sequence Detection

Article - Mar 01, 2020 Asif Ahmad, Abhishek Chauhan - Agnisys

In this era of automation, significant advantages can be gained by automatically generating verification and validation sequences from natural language text using artificial intelligence (AI) based sequence detection techniques, and then using those sequences in C/UVM code. This article talks about the current state of development in this area and gives ideas about how you can implement your own solution to achieve true specification-driven software development.
An Open Data Management Tool for Design and Verification

Article - Mar 01, 2020 Vishal Patel, Manoj Pandey - Arastu Systems

The Big Data technology has evolved to handle both volume and velocity of data, currently being generated by the chip design and verification activities. The core challenge of effective data management and hence actionable insight generation is still not available to the industry in the true sense. Connecting data islands as created by various tools in various formats across digital design and verification workflows and creating a Unified Data Lake is an important missing piece.
Detecting Security Vulnerabilities in a RISC-V® Based System-on-Chip

Article - Mar 01, 2020 Dr. Nicole Fern - Tortuga Logic

Modern electronic systems are complex, and economics dictate that the design, manufacturing, testing, integration and deployment of Application Specific Integrated Circuits (ASICs), System on Chips (SoCs) and Field Programmable Gate Arrays (FPGAs) span companies and countries. Security and trust in this diverse landscape of 3rd party IP providers, processor vendors, SoC integrators and fabrication facilities, is both challenging and introduces security risks.
Formal Verification of RISC-V® Processors

Article - Mar 01, 2020 Dr. Ashish Darbari

The verification of modern-day processors is a non-trivial exercise, and RISC-V® is no exception. In this article, we present a formal verification methodology for verifying a family of RISC-V® “low-power” processors. Our methodology is both new and unique in the way we address the challenges of verification going beyond just functional verification.
Part 10: IC/ASIC Language and Library Adoption Trends

Resource (Verification Horizons Blog) - Jan 20, 2020 Harry Foster

In this blog, I plan to discuss various IC/ASIC language and library adoption trends. Figure 10-1 shows the aggregated adoption trends for languages used to create RTL designs across all market segments and all regions of the world. We see continual interest in SystemVerilog for RTL creation.
Tackling Random Blind Spots with Strategy-Driven Stimulus Generation

Article - Jan 07, 2020 Matthew Ballance
Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPF

Article - Jan 07, 2020 Joe Hupcey
Low Power Apps: Shaping the Future of Low Power Verification

Article - Jan 07, 2020 Verification News