Using Questa® SLEC to Speed Up Verification of Multiple HDL Outputs
Codasip, the leading provider of configurable RISC-V® IP, has come up with a new use of this tool: the verification team uses it to compare a fully UVM-verified HDL code, for example Verilog, with a new HDL output, such as SystemVerilog or VHDL, making sure that they are functionally identical – in a fraction of the time needed before. Total time required for full verification of a new processor design is then reduced by up to 66%, depending on the desired number of HDL output
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