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Welcome once again to our DVCon-US edition of Verification Horizons. I must confess that it feels strange not to be able to write about how the New England Patriots did in the Super Bowl this year since, after three consecutive appearances (winning two, by the way), the Patriots did not make it to the championship game this season. The bigger topic of football conversation around here is whether Tom Brady, our Greatest-of-all-Time quarterback for the past 20 seasons, will sign a new contract and return to the Patriots or will instead decide to sign with another team. Given that he’s made over $200 million in his career, and is married to one of the highest-paid super models in the world, I’m pretty sure his decision won’t be based just on money.

In addition to having played only for the Patriots, Brady also has the distinction of having played for the same head coach, Bill Belichick (also considered the Greatest-of-all-Time) for his entire career. As a result, there has been an ongoing discussion among football fans as to whether Brady’s success is due more to his own talent and work ethic or to Belichick’s coaching. If Brady signs with another team and isn’t as successful – which is common for 43-year-old quarterbacks – then everyone will judge that Belichick was the main reason for his success.

Similarly, if Brady is successful with another team, then it could be argued that Belichick owes his success to Brady. It seems to me that they each have incentive to stay together. Perhaps they would both benefit from the advice of John Wooden, legendary UCLA basketball coach, who said, “It is amazing how much can be accomplished if no one cares who gets the credit.”

In the spirit of getting our jobs done regardless of the credit, we have some great articles for you this time. Our first, from our friends at VerifWorks, is “Verify Thy Verifyer,” where they share some real-life use cases of typical UVM coding issues, from functionality to debug to performance. You’ll not only learn some useful tricks and pitfalls to avoid, but the article also introduces their automated rule checker that helps identify strengths and weaknesses in your UVM code.

Our next article, from Codasip, provides a case study of how they use Questa Sequential Logic Equivalence Checker (SLEC) to accelerate their verification flow. Using a standard UVM environment to verify the functionality of a given processor implementation, they then use Questa® SLEC to compare other implementations of the same processor, thereby shortening the verification of the new implementations from tens of hours to just minutes. You’ll also learn a nice technique for handling large hierarchical designs through decomposition.

In our next article, our friends from Agnisys take us beyond the typical realm of functional verification to discuss “AI Based Sequence Detection.” The article provides a fascinating overview of Deep Learning and other techniques used for Natural Language Processing, which they then apply to typical text-based specifications to auto-generate sequences and assertions to implement the requirements. Even if you don’t use their tool, you’ll learn a lot about AI.

Like AI, Big Data is becoming more prominent in the area of verification. Our friends at Arastu Systems share their thoughts on “An Open Data Management Tool for Design and Verification,” where they discuss the requirements for a tool that will allow effective data management for our industry. I’ve said for years that the key to verification effectiveness is to turn data into information, and that is even more important in the realm of Big Data. This article will show you some ideas that will affect these kinds of large projects.

Our final two articles discuss different strategies for verifying RISC-V® based designs. In “Detecting Security Vulnerabilities in a RISC-V® Based System-on-Chip,” our friends from Tortuga Logic share their experience in winning last year’s Hack@DAC contest by successfully detecting and reporting security bugs in an RTL RISC-V® based SoC. In addition to a useful overview of some of the common security-based issues faced in such a design, you’ll see how their Radix™ tool automates the analysis and generation of checkers for security-related functionality.

If you’re more of a Formal Verification aficionado, our friends at Axiomise share some insights into their Formal Proof Kit® for “Formal Verification of RISC-V® Processors.” This article provides a good overview of common architectural issues you’ll encounter with RISC-V® and shows how a formal tool like Questa PropCheck can be used to detect these kinds of bugs early in the design cycle.

If you’re reading this issue of Verification Horizons at DVCon-US, please stop by the Verification Academy booth and say hi. I’ll be the one with all the extra ribbons on my badge. I look forward to seeing you there.

Respectfully submitted,

Tom Fitzpatrick
Editor, Verification Horizons