Design Verification is a field that requires a lot of thinking and equally a lot of coding. Tighter time-to-market adds a lot of schedule pressure to the teams coding those testbenches and test cases.
The advent of UVM (Universal Verification Methodology) as the standard framework, has helped the industry make good progress in terms of structured testbenches. One of the primary objectives of UVM is to build robust, reusable testbenches. UVM has a set of guidelines on how to build reusable components and also provides a Base Class Library (BCL) that implements basic infrastructure.
As with any code development, verifying the code for compliance, quality and of-course functionality is a tedious task, but a much needed one. In this article we share our experience in helping customers use an innovative technology named Karuta to perform rule-checking on the UVM code base.
EXPECTATIONS FROM A GOOD UVM-BASED TESTBENCH
With UVM now a mature technology, there are several expectations on teams using UVM from its benefits standpoint.
Management Expectations on UVM
Management expects high quality code that can be reused across generations of products. Time-to-market (TTM) is a key metric that management tracks on every project. Another key management concern is the cost of developing and maintaining the UVM code base especially the lower level code. The cost factor drives much of the code to be delegated to junior engineers.