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Courtines and COCOTB Testbench Code

Resource (Tarball) - Dec 14, 2021 by Ray Salemi

This Git repository contains the working code used as examples in the "Python for Verification" Verification Horizons Blog posts.
Exhaustive Trust & Security Verification by Leveraging Emerging Standards

Resource (Recording) - Dec 08, 2021 by John Hallman
Exhaustive Trust & Security Verification by Leveraging Emerging Standards

Resource (Slides (.PDF)) - Dec 08, 2021 by John Hallman
Validation of Complex Safety Architectures

Webinar - Nov 18, 2021 by Vedant Garg

This session explains the methodology and flow of how to perform an accurate safety analysis, followed by fault simulation on the SoC or IP with a combination of hardware and software safety mechanisms.
The UVM Factory

Resource (Verification Horizons Blog) - Nov 17, 2021 by Ray Salemi

The pyuvm implements the UVM factory as it is described in the specification, removing elements that complicated the factory because of SystemVerilog typing.
How Do You Qualify Tools for DO-254

Resource (Paper (.PDF)) - Nov 14, 2021 by Michelle Lange, Tammy Reeve - Patmos Engineering Services

This paper describes the terminology and requirements related to tool qualification specific to the safety-critical programs governed by DO-254 compliance.
How Do You Qualify Tools for DO-254

Paper - Nov 14, 2021 by Michelle Lange, Tammy Reeve - Patmos Engineering Services

This paper describes the terminology and requirements related to tool qualification specific to the safety-critical programs governed by DO-254 compliance. It also provides some practical examples of tool qualification processes and strategies for commonly used tools.
Formal 101: Data Independence and Non-Determinism Made Easy

Session - Nov 11, 2021 by Jin Hou

In this session, we will show how with a little design knowledge and forethought on your part, you can leverage these two principles to cut down your formal analysis to a matter of minutes vs. hours.
Data Independence and Non-Determinism Made Easy

Resource (Slides (.PDF)) - Nov 11, 2021 by
How to Finish Faster with Hierarchical CDC+RDC Methodologies

Resource (Slides (.PDF)) - Nov 02, 2021 by Kurt Takara

In this session, you will learn how to properly deploy hierarchical methodologies in CDC and RDC verification such that neither accuracy nor the performance expected from a hierarchical flow is compromised.
Acceleration Without Compromise: How to Finish Faster with Hierarchical CDC+RDC Methodologies

Webinar - Nov 02, 2021 by Kurt Takara

In this session, you will learn how to properly deploy hierarchical methodologies in CDC and RDC verification such that neither accuracy nor the performance expected from a hierarchical flow is compromised.
The Configuration Database in PYUVM

Resource (Verification Horizons Blog) - Oct 27, 2021 by Ray Salemi

Now we turn our attention to some of the UVM’s utilities and how we use them in Python. The first of these is the UVM configuration database.
Improving Your SystemVerilog Language and UVM Methodology Skills

Track - Oct 27, 2021 by Chris Spear

If you are building complex testbenches with SystemVerilog and UVM, this series is for you. The series dives into many aspects of these two areas, to give you deeper insight about how to apply the language and methodology on your projects. Whether you are new to SystemVerilog and UVM, or have been writing code for many years, take a fresh look at the fundamentals and learn some new ideas and approaches.
CDC Philosophy: The Existential Questions of Constraints, Waivers, and Truth

Webinar - Oct 12, 2021 by Kurt Takara

In this session we will increase your confidence that the CDC results you see are truly reflective of the quality of your design. Using automated assertion-based verification flows and other verification techniques, the designer can know that the constraints and waivers applied are applied correctly.
CDC Philosophy: The existential questions of constraints, waivers, and truth

Resource (Slides (.PDF)) - Oct 12, 2021 by Kurt Takara

In this session we will increase your confidence that the CDC results you see are truly reflective of the quality of your design. Using automated assertion-based verification flows and other verification techniques, the designer can know that the constraints and waivers applied are applied correctly.
TLM 1.0 in pyuvm

Resource (Verification Horizons Blog) - Oct 01, 2021 by Ray Salemi

We’ll examine pyuvm’s implementation TLM 1.0 using simple producer/consumer examples. First, we’ll handle blocking operations.
Formal 101: Exhaustive Scoreboarding and Data Integrity Verification Made Easy

Session - Sep 28, 2021 by Mark Eslinger

In this session, we will show you how to use IEEE standard property checking code (SVA) and off-the-shelf formal tools to quickly and exhaustively verify data transport through the DUT matches the specification.
Exhaustive Scoreboarding and Data Integrity Verification Made Easy

Resource (Slides (.PDF)) - Sep 28, 2021 by
Improving Initial RTL Quality

Webinar - Sep 15, 2021 by Chris Giles

This session will help you lower risks and improve team agility and development consistency by optimizing verification. Using designer-driven verification flows, designers get intent-focused insight to find issues when they are cheapest and easiest to fix.
Improving Initial RTL Quality | Japanese

Resource (Japanese Translation Slides (.PDF)) - Sep 15, 2021 by Chris Giles

This session will help you lower risks and improve team agility and development consistency by optimizing verification. Using designer-driven verification flows, designers get intent-focused insight to find issues when they are cheapest and easiest to fix.
Improving Initial RTL Quality

Resource (Slides (.PDF)) - Sep 15, 2021 by Chris Giles

This session will help you lower risks and improve team agility and development consistency by optimizing verification. Using designer-driven verification flows, designers get intent-focused insight to find issues when they are cheapest and easiest to fix.
Questa AutoCheck: Advanced Linting

Demo - Sep 14, 2021 by Mark Eslinger

This session demonstrates the Questa AutoCheck advanced linting tool and how it can be used with Questa Lint and Questa X-Check for a full suite of RTL checks without a testbench.
Questa X-Check: Identify "X" Issues

Demo - Sep 14, 2021 by Mark Eslinger

This session demonstrates how the Questa X-Check tool can identify X issues without any simulation, complementing Questa Lint and AutoCheck for a full suite of RTL checks.
Questa Lint - Find and Fix RTL Issues

Demo - Sep 14, 2021 by Tom Carlstedt-Duke

This session demonstrates how Questa Lint is used to find and fix RTL issues without a testbench or constraints.
Questa CDC Verification

Demo - Sep 14, 2021 by Kurt Takara

This session demonstrates the Questa CDC Verification comprehensive solution to clock-domain verification.