Resolving Metastability Issues for Multi-clock SoC Environment for I2C
This article aims to resolve metastability issues for multi-clock designs by noting the clock domains and the synchronization required for crossing the clock domains. The example SoC has an 8-bit simple Microcontroller and a Memory Module with a clock differently aligned (multi-clock) to the I2C Master and Slave. Leading to issues regarding metastability that needed to be resolved using synchronizers – currently two flip-flops using a closed-loop solution for sending and receiving clock domains.
