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November 2016

USB Type-C Verification: Challenges and Solution
Simulation Nov 10, 2016 Verification Horizons Article
How to Get the Maximum Out of Your Assertion and Coverage Based Verification Methodology
Standards Nov 10, 2016 Verification Horizons Article
24x7 Productivity: Veloce® Enterprise Server App Does the Job
Acceleration Nov 07, 2016 Vijay Chobisa Article
Power Aware Libraries: Standardization and Requirements for Questa Power Aware
Low Power Nov 07, 2016 Progyna Khondkar Article
Improving Performance and Verification of a System Through an Intelligent Testbench
Simulation Nov 07, 2016 Umesh Patel, Dhaval Shah - Arastu Systems Pvt. Ltd. Article

October 2016

Functional Verification Study - 2016
Planning, Measurement and Analysis Oct 14, 2016 Harry Foster Session

September 2016

Virtualization Delivers Total Verification of SoC Hardware, Software, and Interfaces
Simulation Sep 26, 2016 Verification Horizons Article
Advanced Verification for All: SV/UVM, UCIS, UPF Made Easy
UVM - Universal Verification Methodology Sep 09, 2016 Gordon Allan Webinar

August 2016

Power Aware CDC Verification of Dynamic Frequency and Voltage Scaling (DVFS) Artifacts
Clock-Domain Crossing Aug 26, 2016 Kurt Takara Paper
Power Aware CDC Verification of Dynamic Frequency and Voltage Scaling (DVFS) Artifacts
Clock-Domain Crossing Aug 26, 2016 Kurt Takara pdf
Extending a Traditional VIP to Solve PHY Verification Challenges
Verification IP Aug 26, 2016 pdf
Beyond UVM Registers - Better, Faster, Smarter
UVM - Universal Verification Methodology Aug 25, 2016 Rich Edelman Paper
Beyond UVM Registers - Better, Faster, Smarter
UVM - Universal Verification Methodology Aug 25, 2016 Rich Edelman pdf
Total Recall - What to Look for in a Memory Model Library
Verification IP Aug 24, 2016 pdf
SystemVerilog Code Examples
SystemVerilog Aug 24, 2016 Ray Salemi zip
Article: How to instrument your design with simple SystemVerilog assertions
Standards Aug 24, 2016 link
SystemVerilog & UVM Coding & Performance Guidelines
SystemVerilog Aug 24, 2016 pdf
Technical Paper: A Scalable Approach for TLM Across SystemC and SystemVerilog
Standards Aug 24, 2016 pdf
Technical Paper: Towards an Object-Oriented Design Methodology Using SystemVerilog
Standards Aug 24, 2016 pdf
SystemVerilog Performance Guide
SystemVerilog Aug 24, 2016 pdf
SystemVerilog Assertions Design Tricks & SVA Bind Files (slide set 4)
Standards Aug 24, 2016 pdf
SystemVerilog Coding Guide
SystemVerilog Aug 24, 2016 pdf
Technical Paper: Binding SystemVerilog to VHDL Components Using Questa
Standards Aug 24, 2016 pdf
Technical Paper: TLM2 in SystemVerilog
Standards Aug 24, 2016 pdf
Technical Paper: Planning SystemVerilog Adoption
Standards Aug 24, 2016 pdf

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November 2016

USB Type-C Verification: Challenges and Solution

How to Get the Maximum Out of Your Assertion and Coverage Based Verification Methodology

24x7 Productivity: Veloce® Enterprise Server App Does the Job

Power Aware Libraries: Standardization and Requirements for Questa Power Aware

Improving Performance and Verification of a System Through an Intelligent Testbench

October 2016

Functional Verification Study - 2016

September 2016

Virtualization Delivers Total Verification of SoC Hardware, Software, and Interfaces

Advanced Verification for All: SV/UVM, UCIS, UPF Made Easy

August 2016

Power Aware CDC Verification of Dynamic Frequency and Voltage Scaling (DVFS) Artifacts

Power Aware CDC Verification of Dynamic Frequency and Voltage Scaling (DVFS) Artifacts

Extending a Traditional VIP to Solve PHY Verification Challenges

Beyond UVM Registers - Better, Faster, Smarter

Beyond UVM Registers - Better, Faster, Smarter

Total Recall - What to Look for in a Memory Model Library

SystemVerilog Code Examples

Article: How to instrument your design with simple SystemVerilog assertions

SystemVerilog & UVM Coding & Performance Guidelines

Technical Paper: A Scalable Approach for TLM Across SystemC and SystemVerilog

Technical Paper: Towards an Object-Oriented Design Methodology Using SystemVerilog

SystemVerilog Performance Guide

SystemVerilog Assertions Design Tricks & SVA Bind Files (slide set 4)

SystemVerilog Coding Guide

Technical Paper: Binding SystemVerilog to VHDL Components Using Questa

Technical Paper: TLM2 in SystemVerilog

Technical Paper: Planning SystemVerilog Adoption