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January 2017

So You Think You Have Good Stimulus: System-Level Distributed Metrics Analysis and Results
Simulation Jan 03, 2017 Andreas Meyer Article
Are You Really Confident That You Are Getting the Very Best From Your Verification Resources?
Verification Management Jan 03, 2017 Darron May Article
Bringing Regression Systems into the 21st Century
Verification Management Jan 03, 2017 Thom Ellis Article

December 2016

Jenkins Tutorial - Setup, Install, Configuration
Planning, Measurement and Analysis Dec 23, 2016 Darron May pdf
JUnit Plugin (required)
Planning, Measurement and Analysis Dec 23, 2016 link
Questa VRM
Planning, Measurement and Analysis Dec 23, 2016 Darron May link
Jenkins Release
Planning, Measurement and Analysis Dec 23, 2016 link
Dashboard View (optional)
Planning, Measurement and Analysis Dec 23, 2016 link
Best Practices for FPGA and ASIC Development
Simulation Dec 21, 2016 Verification Horizons Article
Five Common Pitfalls To Avoid While Verifying PCIe® Based NVMe Controllers
Verification IP Dec 19, 2016 Saurabh Sharma Paper
Five Common Pitfalls to Avoid while Verifying PCIe Based NVMe Controllers
Verification IP Dec 19, 2016 Saurabh Sharma pdf
Verifying Display Standards – A Comprehensive UVM-based Verification IP Solution
Verification IP Dec 19, 2016 Saumya Agrawal Paper
Verifying Display Standards – A Comprehensive UVM-based Verification IP Solution
Verification IP Dec 19, 2016 Saumya Agrawal pdf
The Fundamental Power States for UPF Modeling and Power Aware Verification
Low Power Dec 14, 2016 Progyna Khondkar pdf
The Fundamental Power States for UPF Modeling and Power Aware Verification
Low Power Dec 14, 2016 Progyna Khondkar Paper
What Is CDC Protocol Verification, Prevent Bugs in Your Silicon
Clock-Domain Crossing Dec 05, 2016 Kurt Takara Webinar
What Is CDC Protocol Verification, Prevent Bugs in Your Silicon
Clock-Domain Crossing Dec 05, 2016 Kurt Takara pdf
How to Shorten Your Schedule with Interactive Formal Debug and Design Exploration
Formal Verification Dec 05, 2016 Mark Eslinger Webinar

November 2016

FPGA Prototyping: Maximize Your Enterprise Debug Productivity
Debug Nov 11, 2016 Stephen Bailey Webinar
Industry Trends in Today’s Functional Verification Landscape
Planning, Measurement and Analysis Nov 11, 2016 Harry Foster Webinar
Enterprise Verification Debug and Analysis
Debug Nov 11, 2016 Stephen Bailey Webinar
System Level Debug & Analysis
Debug Nov 11, 2016 Gordon Allan Webinar
Enterprise Debug for Formal
Formal Verification Nov 11, 2016 Joe Hupcey Webinar
Enterprise Debug for Simulation
Debug Nov 11, 2016 Moses Satyasekaran Webinar
INs and OUTs of CAN Verification—A Comprehensive UVM-based Solution
Standards Nov 10, 2016 Verification Horizons Article

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January 2017

So You Think You Have Good Stimulus: System-Level Distributed Metrics Analysis and Results

Are You Really Confident That You Are Getting the Very Best From Your Verification Resources?

Bringing Regression Systems into the 21st Century

December 2016

Jenkins Tutorial - Setup, Install, Configuration

JUnit Plugin (required)

Questa VRM

Jenkins Release

Dashboard View (optional)

Best Practices for FPGA and ASIC Development

Five Common Pitfalls To Avoid While Verifying PCIe® Based NVMe Controllers

Five Common Pitfalls to Avoid while Verifying PCIe Based NVMe Controllers

Verifying Display Standards – A Comprehensive UVM-based Verification IP Solution

Verifying Display Standards – A Comprehensive UVM-based Verification IP Solution

The Fundamental Power States for UPF Modeling and Power Aware Verification

The Fundamental Power States for UPF Modeling and Power Aware Verification

What Is CDC Protocol Verification, Prevent Bugs in Your Silicon

What Is CDC Protocol Verification, Prevent Bugs in Your Silicon

How to Shorten Your Schedule with Interactive Formal Debug and Design Exploration

November 2016

FPGA Prototyping: Maximize Your Enterprise Debug Productivity

Industry Trends in Today’s Functional Verification Landscape

Enterprise Verification Debug and Analysis

System Level Debug & Analysis

Enterprise Debug for Formal

Enterprise Debug for Simulation

INs and OUTs of CAN Verification—A Comprehensive UVM-based Solution