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Solutions

The Verification Academy Solutions section delivers focused insights into key market segments and verification products that address today’s emerging challenges. Explore how advanced technologies and methodologies—spanning functional verification, safety, security, and more—are applied to solve real-world design problems. This curated content brings together best practices, expert perspectives, and proven tools to accelerate verification success.
Techniques

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Techniques

Design for Test Verification

Safety & Security

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Methodology

Unified Coverage

Design for Test Verification

Accelerating DFT Sign-Off with Questa One

Tackling Emerging DFT Verification Challenges with Questa One

Functional Safety

Functional Safety for ISO 26262

Functional Safety for DO-254

Unified Coverage

Questa One Unified Coverage Solution: Transforming Verification Through Intelligence

Boost Your Verification Productivity with Questa Verification IQ

Coverage Closure Acceleration Using Collaborative Verification IQ Tool

Functional Safety for ISO 26262

Accelerated Assurance with Questa One Functional Safety

Functional Safety for DO-254

Introduction to DO-254
Topics

The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.
UVM

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Simulation

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Questa Design Solutions

Clock-Domain Crossing

Formal Verification

Reset-Domain Crossing

Verification Management & IP

Verification IQ

Verification IP

Verification Planning
Cookbooks

Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.
UVM

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UVM

UVM Basics

UVM Testbench

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UVM Messaging System

UVM Stimulus Techniques

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UVM Debugging

UVM Connect

Guidelines & Migration

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SystemVerilog Performance

UVM Coding

UVM Performance

UVM 1800.2

UVM 1.2

OVM to UVM

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UVM 1.2

UVM 1.1d

UVM 1.1c

UVM 1.1b

UVM 1.1a

Coverage

Coverage Metrics and Process (Theory)

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From Rule-Based Beginnings to AI-Driven Design: Tracing the Evolution of AI in EDA

DFT Verification: Tackling the Evolving Challenges

Closing the Gap in Software Skills for Verification Engineers

Accellera announces fee-free availability of IEEE Std. 1801™-2024

Got Coverage?

Update from the Standards World: Accellera Approves UVM-MS 1.0 Standard

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Debug

Faster Debug of Complex Testbenches using Visualizer

Win the Tick to Trade Race by Root Causing Bugs Faster with QuestaSim

Prevent Performance Problems with Prompt RTL Profiling

Accelerate Development Using Advanced Debugging Approaches

Formal Verification

Generating SystemVerilog Assertion (SVA) Properties with Property Assist

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Explore How to Protect Against Data Corruption with Formal Security Verification

Questa Formal Verification IP AMBA: Achieve Protocol Compliance in Designs

Functional Verification Workflow for Trusted and Assured Microelectronics

FPGA Verification

Securing your FPGA Design from RTL through to the Bitstream

Improving FPGA Safety and Security Compliance: FPGA Equivalence Checking from RTL to the Bitstream

Bringing Model-based Systems Engineering to IC and FPGA Design

ModelSim to Questa - Productivity Features

Functional Safety

Enhancing Automotive Safety Verification Using Questa One Sim FX

Enhancing Defect Coverage in DFT

Safety Analysis for Automotive Chips Based on ISO 26262

An End-to-End Functional Safety Solution for Automotive ICs Based on ISO 26262

Union of SoC Design & Functional Safety FlowUnion of SoC Design & Functional Safety Flow

Questa Design Solutions

Improving Designer Productivity and Enabling Faster RDC Verification Closure with Machine Learning

New Advanced Techniques for Reset Domain Crossing (RDC) Analysis

Continuous Integration (CI) Driving Efficient Program Execution

Questa Design Solutions as a Sleep Aid

Applying Machine Learning to Accelerate CDC Analysis

Formal and the Next Normal

Questa Lint vs Formal AutoCheck

Simulation

Accelerating Functional Coverage with Questa One CX

Tackling Emerging DFT Verification Challenges with Questa One

Faster Debug Using QuestaSim Interactive Coverage Analysis

Unlocking the Power of QuestaSim and Visualizer Integration

Productivity in the Questa Simulation Flow

SystemVerilog

Introduction to SystemVerilog Assertions

Generating SVA Properties with Property Assist

Easy Test Writing with a Proxy-driven Testbench

Making Your DPI-C Interface a Fast River of Data

The Life of a SystemVerilog Variable

Verification IP

Breaking Barriers: Ethernet 1.6T, Infiniband, UALink, and UEC Verification for Next-Gen Connectivity

PCIe Gen7 Verification with Siemens Avery Verification IP

Verifying the Next Generation High Bandwidth Memory Controllers for AI and HPC Applications

The Future of Multi-Die System Verification with UCIe

Verification IQ

Streamlining Requirements Traceability using Questa Verification IQ Testplan Author

Smart Debug: Accelerate Root Cause Analysis and Reduce Debug Turnaround Time with Questa Verification IQ Regression Navigator

Smart Regression: Optimize Regression Efficiency Using Questa Verification IQ Regression Navigator

Boost Your Verification Productivity with Questa Verification IQ

Questa Verification IQ: Boost Verification Predictability and Efficiency with Big Data

Verification Planning

Solving the Semiconductor Verification Crisis: From Problem to Productivity

Functional Verification Study - 2022

The Three Pillars of Intent-Focused Insight

Trends in Functional Verification

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Browse all content in Siemens Verification Academy with the topic Verification IP

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June 2024

Accelerated Confidence in Interface Designs mixing Software Layers, Hardware Protocols, Physical Connections
Verification IP Jun 24, 2024 Gordon Allan Conference
Challenges of Developing IPs for AI Chips
Verification IP Jun 24, 2024 Tom Fitzpatrick Conference
Learn about the Security-critical CMA/SPDM, DOE, IDE, and TDISP elements of the PCIe protocol at the 2024 PCI SIG DevCon
Verification IP Jun 04, 2024 Joe Hupcey link
The New Leader in Verification IP: Questa + Avery Solutions
Verification IP Jun 04, 2024 Rick Schmidt - Siemens Eda pdf

May 2024

The New Leader in Verification IP: Questa + Avery Solutions
Verification IP May 21, 2024 Kamlesh Mulchandani pdf

April 2024

How We Use PCIe Verification IP Across Multiple Projects
Verification IP Apr 04, 2024 Weiping Guo - Marvell Conference
How We Use PCIe Verification IP Across Multiple Projects
Verification IP Apr 04, 2024 Weiping Guo - Marvell pdf

March 2024

Reduce Gate-level Simulation Bring-up Time with Semi-formal X Verification
Verification IP Mar 27, 2024 Rick Koster pdf
Reduce Gate-level Simulation Bring-up Time with Semi-formal X Verification
Verification IP Mar 27, 2024 Rick Koster Webinar
Enhancing PCIe Verification: How to Step Off the Map
Verification IP Mar 01, 2024 Irivinti Shiva Teja - Siemens Eda Article

February 2024

Comprehensive CXL 3.0 Verification for High-Bandwidth and Low-Latency Connectivity
Verification IP Feb 21, 2024 Chris Browy Webinar

January 2024

Comprehensive PCIe Verification Solution for Bleeding Edge and Mission Critical SoC & IP Designs
Verification IP Jan 24, 2024 Luis Rodriguez pdf
Comprehensive PCIe Verification Solution for Bleeding Edge and Mission Critical SoC & IP Designs
Verification IP Jan 24, 2024 Luis Rodriguez Webinar

December 2023

Multi-Die System Verification with Siemens’s UCIe VIP
Verification IP Dec 07, 2023 Justin Bunnell pdf
Multi-Die System Verification with Siemens’s UCIe VIP
Verification IP Dec 07, 2023 Justin Bunnell Webinar

June 2023

The New Leader in Verification IP: Questa + Avery Solutions
Verification IP Jun 06, 2023 Gordon Allan pdf

April 2023

Delivering First Silicon Success for Your Next SoC or 3DIC
Verification IP Apr 25, 2023 Gordon Allan pdf
Delivering First Silicon Success for Your Next SoC or 3DIC
Verification IP Apr 25, 2023 Gordon Allan Webinar

February 2023

Lane Margining at Receiver and its Application Through Pipe Message Bus
Verification IP Feb 24, 2023 Sachin Mishra Article
The RISC-V Verification Interface (RVVI) – Test Infrastructure and Methodology Guidelines
Verification IP Feb 24, 2023 Aimee Sutton, Lee Moore, Kevin Mcdermott - Imperas Software Article

December 2022

Effective Resource Utilization in PCIe® Gen6: Shared Flow Control
Verification IP Dec 01, 2022 Vidushi Goel - Siemens Eda Article
Data Integrity through TLP Encryption in PCI Express®
Verification IP Dec 01, 2022 Om Prakash - Siemens Eda Article

July 2022

Unblocking the Full Potential of SSDs Using Zoned and Key Value Namespaces
Verification IP Jul 05, 2022 Himani Kaushik - Siemens Eda Article

March 2022

NVMe-oF – Simple, Invisible Fabric to Cloud Storage
Verification IP Mar 02, 2022 Dhruv Garg - Siemens Eda Article

September 2021

Verifying a DDR5 Memory Subsystem
Verification IP Sep 01, 2021 Kamlesh Mulchandani Article

26–50 of 107

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