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2026 Functional Verification Study: Executive Findings

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Five Signals from the 2026 Functional Verification Study

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AI in Functional Verification: What the 2026 Industry Data Reveals

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DFT's Expanding Role in Software-Driven Silicon: From Structural Test Closure to System-Assurance Evidence

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February 2026

Don’t Miss CDC Bugs in Low Power Designs!: Formal Meets Power Aware CDC

Close Coverage Faster with Questa One Sim's Unreachability Analysis

Compute Subsystem RTL Signoff with CSS VIP and Software Aware VIP

Securing Next-Generation Interconnects: PCIe® Gen7 Security Verification

Verifying Chiplet Interconnects at Scale: UCIe® 3.0

Verifying Future Accelerator Interconnects: UALink™ Verification IP and Why UALink Matters

January 2026

Achieving Mathematical Certainty in Design Verification with Formal

Cut Weeks From Debug: Rapid First – Level Bug Hunting with Inspect and Check X

Supercharge Your CDC & RDC Analysis with the Power of AI/ML

Simulating CDC Reconvergence: Validating Robustness with Questa One Sim's Metastability Injection

BUGGED OUT Podcast - Episode 3: Chandu Challapalli

New Innovative Way to Functionally Verify Heterogeneous 2D/3D Package Connectivity

Formal Verification Made Simple: A Practical Guide for FPGA Designers

Constrained Randomization and Functional Coverage in Questa One Sim with UVVM

System Verifier

December 2025

BUGGED OUT Podcast - FutureCast 2026: Part 2

Formal Verification of Synthesizable C++/SystemC Designs

The Future of Semiconductors: Engineering in the Convergence Era

FutureCast 2026: A Special Holiday Edition of BUGGED OUT

BUGGED OUT Podcast - FutureCast 2026: Part 1

Questa One Smart Verification: Unleashing the Potential of AI Within Functional Verification

Introducing Questa One SFV: The Transformation of Static & Formal Powered by AI/ML

Ensure High Quality RTL with Early Continuous Integration

Enhancing Verification Productivity with Questa One

VA Live - Scottsdale: Introduction and Welcome