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• UVM-based Verification of a RISC-V Processor Core Using a Golden Predictor Model and a Configuration Layer (Article)
• UVM: What's New, What's Next and Why You Care (Webinar)
• UVMC (topic)
• UVMC Command API (Chapter)
• UVMC Connections (Chapter)
• UVMC Conversion (Chapter)
• UVMF & Emulation (Session)
• UVMF - Overview (Session)
• UVMF - Series Introduction (Session)
• UVMF Build/Compile/Run Script Introduction (Session)
• UVMF, Beyond the ALU Generator Tutorial Extending Actual Test Control of the DUT Inputs (Article)
• UVVM – VHDL Verification Methodology for Faster and Better FPGA and ASIC Verification (Article)
• Ujjwal Negi (author)
• Ultra Accelerator Link (UALink) Verification: A Deep Dive with Siemens Avery Verification IP (Webinar)
• Unblocking the Full Potential of SSDs Using Zoned and Key Value Namespaces (Article)
• Understanding Formal Methods for Use in DO-254 Programs (Paper)
• Understanding Low Power Impact on CDC Logic (Session)
• Understanding Metastability (Session)
• Understanding and Using Immediate Assertions (Article)
• Understanding the Factory and Configuration (Session)
• Understanding the SVA Engine Using the Fork-Join Model (Article)
• Understanding the Two Main Testing Approaches (Lesson)
• Understanding the UPF Power Domain and Domain Boundary (Article)
• Unidirectional Protocols (Chapter)
• Unified Approach to Verify Complex FSM (Article)
• Union of SoC Design & Functional Safety Flow (Webinar)
• Unit Testing UVM Components (Session)
• Unit Testing Your Way to a Reliable Testbench (Article)
• Unleashing Portable Stimulus Productivity with a PSS Reuse Strategy (Article)
• Unlocking the Power of QuestaSim and Visualizer Integration (Webinar)
• Use Formal to Check Logic Faults (Webinar)
• Use of Iterative Weight-Age Constraint to Implement Dynamic Verification Components (Article)
• Using Automation to Close the Loop Between Functional Requirements and Their Verification (Webinar)
• Using Formal Analysis to Block and Tackle (Article)
• Using Formal Verification in Daily Work (Webinar)
• Using Messaging (Chapter)
• Using Questa SLEC to Speed Up Verification of Multiple HDL Outputs (Article)
• Using Questa for Pre-silicon Validation of IEEE 1149.1-2013 based Silicon Instruments (Article)
• Using Strong Types in SystemVerilog Design and Verification Environments (Paper)
• Using Supply Sets (Session)
• Using Test-IP Based Verification Techniques in a UVM Environment (Article)
• Using a Parameter Package (Chapter)
• Using the Register Layer (Session)
• Using the UVM Configuration Database (Lesson)
• Using the UVM Factory (Lesson)
• VHDL 2008 (topic)
• VHDL-2008 Overview (Session)
• VHDL-2008 Why It Matters (track)
• VHDL-2008: Why It Matters (Article)
• Vahid Naraghi (author)
• Validation of Complex Safety Architectures (Webinar)
• Vedant Garg (author)
• Veloce Hardware-Assisted Verification – Complete, Unified, and Progressive (Article)
• Veloce Prototyping Solutions Accelerate Verification of HPC AI-Enabled SoCs (Article)
• Verification Academy (author)
• Verification Academy Live: El Segundo (Seminar)
• Verification Academy Live: El Segundo (Seminar)
• Verification Cookbook Glossary (Chapter)
• Verification Data Analytics with Machine Learning (Paper)
• Verification Effectiveness Trends (Session)
• Verification Effort Trends (Session)
• Verification Horizons (Article)
• Verification IP (topic)
• Verification IP Stimulus APIs: Are They Really Easy to Use? (Paper)
• Verification IQ (topic)
• Verification Learns a New Language: An IEEE 1800.2 Python Implementation (Webinar)
• Verification Management (topic)
• Verification Methodology Cookbooks (Cookbook)
• Verification Planning and Management (track)
• Verification Planning with Questa Verification Management (Article)
• Verification Process Overview (Session)
• Verification Technology Trends (Session)
• Verification and Debug: Old School Meets New School (Webinar)
• Verification of a NAND Flash Memory Controller using UVMF and CDC (Conference)
• Verify Thy Verifyer (Article)
• Verifying Display Standards: A Comprehensive UVM-based Verification IP Solution (Paper)
• Verifying Display Standards: A Comprehensive UVM-based Verification IP Solution (Article)
• Verifying High Speed Peripheral IPs (Article)
• Verifying a DDR5 Memory Subsystem (Article)
• Verifying the Evolving UCIe Landscape: A 3.0-Aware Architecture for Manageability and Beyond (Paper)
• Verifying the Next Generation High Bandwidth Memory Controllers for AI and HPC Applications (Webinar)
• Verilog Basics for SystemVerilog Constrained Random Verification (Webinar)
• Verilog Expression Impact on Constraints (Lesson)
• Viewing Data Values (Demo)
• Vigyan Singhal (author)
• Vijay Chobisa (author)
• Vinayak Desai (author)
• Virtual Interface BFMs (Chapter)
• Virtual Method Upcasting & Downcasting And Their Use In UVM (Conference)
• Virtual Sequencers (Not Recommended) (Chapter)
• Virtual Sequences (Chapter)
• Virtualization Delivers Total Verification of SoC Hardware, Software, and Interfaces (Article)
• Visualizer Coverage: Debug and Visualize All Your Coverage (Webinar)
• Visualizer Debug Environment: Class-based Testbench Debugging using a New School Debugger – Debug This! (Article)
• Visualizer: Livesim / Interactive (track)
• Vlada Kalinic (author)
• Vladislav Palfy (author)
• Wait for a Signal (Chapter)
• Walter Gude (author)
• Wave Windows Features (Demo)