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• USB 3.1 Verification Challenges (Seminar)
• USB Type-C Verification: Challenges & Solution (Article)
• UVM (cookbook)
• UVM "Hello World" (Session)
• UVM - Universal Verification Methodology (topic)
• UVM 1.2 is Coming, so be Prepared (Webinar)
• UVM 1800.2 & The New and Improved UVM Cookbook (Webinar)
• UVM Agent (Chapter)
• UVM Basics (track)
• UVM Coding Guidelines: Tips & Tricks You Probably Didn’t Know (Webinar)
• UVM Command API (Session)
• UVM Components (Chapter)
• UVM Components and Tests (Session)
• UVM Configuration Database (Chapter)
• UVM Configuration Database (Chapter)
• UVM Configuration Database Debug (Session)
• UVM Connect (Chapter)
• UVM Connect (track)
• UVM Connectivity Debug (Session)
• UVM Debug (Webinar)
• UVM Debug (track)
• UVM Debug Editor Insight (Session)
• UVM Debug? Beyond Logfiles (Session)
• UVM Driver (Chapter)
• UVM Environments (Session)
• UVM Factory (Chapter)
• UVM Framework (track)
• UVM Framework (topic)
• UVM Framework – Create a UVM Environment in Less than an Hour (Webinar)
• UVM Guidelines (Chapter)
• UVM IEEE Shiny Object (Article)
• UVM Monitor (Chapter)
• UVM Packages (Chapter)
• UVM Performance Guidelines (Chapter)
• UVM Phase Debug (Session)
• UVM Phasing (Chapter)
• UVM Rapid Adoption: A Practical Subset of UVM (Conference)
• UVM Report Catcher (Chapter)
• UVM Reporting (Session)
• UVM Sans UVM: An Approach to Automating UVM Testbench Writing (Article)
• UVM Sequence Items (Chapter)
• UVM Sequences (Chapter)
• UVM Sequences in Depth (Webinar)
• UVM Simulation of MathWorks® Designs at Block, Subsystem, and Chip Level (Conference)
• UVM Stimulus, Tests, and Regressions (Session)
• UVM Test Flow (Lesson)
• UVM Testbench Structure and Coverage Improvement in a Mixed Signal Verification Environment (Article)
• UVM Tips and Tricks (Article)
• UVM Verification Component (Chapter)
• UVM and C Tests - Perfect Together (Article)
• UVM-based Verification of a RISC-V Processor Core Using a Golden Predictor Model and a Configuration Layer (Article)
• UVM: What's New, What's Next and Why You Care (Webinar)
• UVMC (topic)
• UVMC Command API (Chapter)
• UVMC Connections (Chapter)
• UVMC Conversion (Chapter)
• UVMF & Emulation (Session)
• UVMF - Overview (Session)
• UVMF - Series Introduction (Session)
• UVMF Build/Compile/Run Script Introduction (Session)
• UVMF, Beyond the ALU Generator Tutorial Extending Actual Test Control of the DUT Inputs (Article)
• UVVM – VHDL Verification Methodology for Faster and Better FPGA and ASIC Verification (Article)
• Ujjwal Negi (author)
• Ultra Accelerator Link (UALink) Verification: A Deep Dive with Siemens Avery VIP (Webinar)
• Unblocking the Full Potential of SSDs Using Zoned and Key Value Namespaces (Article)
• Understanding Formal Methods for Use in DO-254 Programs (Paper)
• Understanding Low Power Impact on CDC Logic (Session)
• Understanding Metastability (Session)
• Understanding and Using Immediate Assertions (Article)
• Understanding the Factory and Configuration (Session)
• Understanding the SVA Engine Using the Fork-Join Model (Article)
• Understanding the Two Main Testing Approaches (Lesson)
• Understanding the UPF Power Domain and Domain Boundary (Article)
• Unidirectional Protocols (Chapter)
• Unified Approach to Verify Complex FSM (Article)
• Union of SoC Design & Functional Safety Flow (Webinar)
• Unit Testing UVM Components (Session)
• Unit Testing Your Way to a Reliable Testbench (Article)
• Unleashing Portable Stimulus Productivity with a PSS Reuse Strategy (Article)
• Unlocking the Power of QuestaSim and Visualizer Integration (Webinar)
• Use Formal to Check Logic Faults (Webinar)
• Use of Iterative Weight-Age Constraint to Implement Dynamic Verification Components (Article)
• Using Automation to Close the Loop Between Functional Requirements and their Verification (Webinar)
• Using Formal Analysis to Block and Tackle (Article)
• Using Formal Verification in Daily Work (Webinar)
• Using Messaging (Chapter)
• Using Questa SLEC to Speed Up Verification of Multiple HDL Outputs (Article)
• Using Questa for Pre-silicon Validation of IEEE 1149.1-2013 based Silicon Instruments (Article)
• Using Strong Types in SystemVerilog Design and Verification Environments (Paper)
• Using Supply Sets (Session)
• Using Test-IP Based Verification Techniques in a UVM Environment (Article)
• Using a Parameter Package (Chapter)
• Using the Register Layer (Session)
• Using the UVM Configuration Database (Lesson)
• Using the UVM Factory (Lesson)
• VHDL 2008 (topic)
• VHDL-2008 Overview (Session)
• VHDL-2008 Why It Matters (track)
• VHDL-2008: Why It Matters (Article)
• Vahid Naraghi (author)