UVM Connect
UVM Connect will demonstrate how to reuse your SystemC architectural models and/or reuse SystemVerilog UVM agents to verify models in SystemC.
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Sessions
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Introduction to UVM Connect
This session introduces UVM Connect and explains the benefits of adoption. -
Connections
This session shows how to establish connections between components. -
Converters
This session shows how to write the converters that are needed to transfer transaction data. -
UVM Command API
This session shows how control key aspects of UVM simulation from SystemC.
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UVM Connect Overview
UVM Connect is an open-source UVM-based library that provides TLM1 and TLM2 connectivity and object passing between SystemC and SystemVerilog UVM models and components.
It also provides a UVM Command API for accessing and controlling UVM simulation from SystemC (or C or C++). UVM Connect allows you to reuse your SystemC architectural models as reference models in UVM verification and/or reuse SystemVerilog UVM agents to verify models in SystemC.
It also effectively expands your VIP portfolio since you now have access to VIP in both languages. UVM Connect allows you easily to develop integrated verification environments where you take advantage of the strengths of each language to maximize your verification productivity.
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UVM Connect 2.3.3
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UVM Connect Cookbook
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