Browse all content in Verification Academy: Articles, Cookbooks, Resources, Sessions, and Tracks

November 2025

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  HLV – Formal Verification of Synthesizable C++/SystemC Designs

  Formal Verification Nov 05, 2025 Vlada Kalinic Webinar

May 2025

• SLEC System Flow: Leveraging Formal in Math Primitive Verification Closure

  Formal Verification May 01, 2025 Abhiram Dronavalli - Microsoft pdf

August 2024

• UVM Connect 2.3.4 Kit

  UVMC Aug 29, 2024 John Stickley tar

• UVM Connect 2.3.4 Primer

  UVMC Aug 29, 2024 John Stickley pdf

• UVM Connect 2.3.4 Release Notes

  UVMC Aug 29, 2024 John Stickley txt

December 2023

• IEEE Honors Siemens Employees for Dedication to Standards Development

  Standards Dec 12, 2023 Tom Fitzpatrick link

• UVM Connect 2.3.3 Kit

  UVMC Dec 11, 2023 John Stickley tar

• UVM Connect 2.3.3 Primer

  UVMC Dec 11, 2023 John Stickley pdf

• UVM Connect 2.3.3 HTML

  UVMC Dec 11, 2023 John Stickley tar

November 2023

• Reducing Formal Verification Runtime in SystemC Utilizing Modular Interface

  Formal Verification Nov 16, 2023 Hideki Kazama - Sony pdf

• Reducing Formal Verification Runtime in SystemC Utilizing Modular Interface

  Formal Verification Nov 16, 2023 Hideki Kazama - Sony mp4

May 2022

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  UVM Connect

  UVMC May 23, 2022 Adam Erickson Track

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  Accelerate Development Using Advanced Debugging Approaches

  Debug May 10, 2022 Rich Edelman Webinar

March 2022

• Why Not Connect Using UVM Connect: Mixed Language Communication Got Easier with UVMC

  UVMC Mar 23, 2022 Vishal Baskar mp4

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  Why Not Connect Using UVM Connect: Mixed Language Communication Got Easier with UVMC

  UVMC Mar 23, 2022 Vishal Baskar Paper

• Why Not Connect Using UVM Connect: Mixed Language Communication Got Easier with UVMC

  UVMC Mar 23, 2022 Vishal Baskar pdf

March 2021

• Early Design Validation AI Accelerator’s System Level Performance Using An HLS Design Methodology

  High-Level Synthesis Mar 31, 2021 Michael Fingeroff - Siemens Eda pdf

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  Early Design & Validation of an AI Accelerator’s Performance Using an HLS Design

  High-Level Synthesis Mar 31, 2021 Michael Fingeroff - Siemens Eda Seminar

November 2019

• UVMC 2.3.2 Library

  UVMC Nov 15, 2019 html

• UVM Connect 2.3.2 Kit

  UVMC Nov 14, 2019 John Stickley tar

• UVM Connect 2.3.2 Primer

  UVMC Nov 14, 2019 John Stickley pdf

• UVM Connect 2.3.2 HTML

  UVMC Nov 14, 2019 John Stickley tar

August 2019

• Machine-Learning-Assisted Agile VLSI Design for Machine Learning

  Machine Learning Aug 31, 2019 Brucek Khailany link

June 2019

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  SystemC FMU for Verification of Advanced Driver Assistance Systems

  Functional Safety Jun 03, 2019 Keroles Khalil, Magdy A. El-Moursy - Siemens Eda Article

November 2017

• UVM Connect 2.3.1 Primer

  UVMC Nov 08, 2017 John Stickley tar