Early Design Validation AI Accelerator’s System Level Performance Using An HLS Design Methodology
This workshop will demonstrate how pre-hls simulation using MatchLib can identify and fix potential system-level performance issues that are normally not found till very late in a hand-coded RTL design methodology.
Full-access members only
Register your account to view Early Design Validation AI Accelerator’s System Level Performance Using An HLS Design Methodology
Full-access members gain access to our free tools and training, including our full library of articles, recorded sessions, seminars, papers, learning tracks, in-depth verification cookbooks, and more.