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2150 Results

  • Verification Academy Live: Scottsdale

    Seminar - Dec 03, 2025 by Joe Hupcey

    This seminar will update you on technologies and techniques to increase your verification productivity today. How the new AI/ML paradigm shift across the industry is enabling functional verification productivity gains The benefits of an automated Continuous Integration flow to enhance RTL quality and streamline development processes The latest advancements in the RTL simulation Wednesday, December 3, 2025 | 9:30 AM - 5:00 PM Location TopGolf 9500 E. Talking Stick Way Scottsdale, AZ 85256

  • Debug Like a Pro: VHDL Testbenches with OSVVM, UVVM, & UVM in Questa One Sim

    Webinar - Dec 03, 2025 by Mariam Maurice

    This webinar explores the debugging capabilities and best practices across the three leading VHDL verification (OSVVM, UVVM, UVM) frameworks.

  • Aerospace & Defense

    Reference - Nov 19, 2025 by

    Welcome to the Aerospace and Defense event archive, where you will find presentations and slide decks from live events that you may have missed. *Please note: you will need a valid login to download the session presentations.

  • Questa One Avery Verification IP: Delivering Accelerated Confidence

    Resource (Slides (.PDF)) - Nov 19, 2025 by Luis Rodriguez

    In this session, you will learn how Questa One Avery VIP’s cutting-edge technologies promise to enhance productivity and ease of use in the rapidly expanding landscape of complex interfaces and memory protocols, spanning SoC designs, 3DIC chiplets, and FW/SW integration.

  • Enhancing Verification Productivity with Questa One Sim

    Resource (Slides (.PDF)) - Nov 19, 2025 by Sunil Sahoo

    In this session, you will learn how Questa One Sim’s productivity-driven approach ensures resources are deployed effectively, accelerating verification closure.

  • MARLUG - 2025

    Seminar - Nov 19, 2025 by Sunil Sahoo

    User2User Mid-Atlantic is your opportunity to learn, grow and connect with fellow technical experts who design leading-edge electronics products using Siemens EDA tools.

  • System Testbench with Questa Parallelsim

    Resource (Slides (.PDF)) - Nov 19, 2025 by John Liu - Northrop Grumman

    In this session, you will learn how Questa ParallelSim processing significantly improves test efficiency and performance in a complex multichip FPGA system.

  • Don't Let VHDL Debugging Slow You Down! Use Questa One Sim

    Webinar - Nov 12, 2025 by Nicole Munson

    In this webinar, you will learn how Questa One Sim  empowers VHDL designers to dramatically enhance their debugging productivity. We'll move beyond basic simulation viewing and dive into advanced features designed to pinpoint issues faster, understand design behavior more intuitively, and streamline your entire VHDL RTL debug workflow.

  • Don't Let VHDL Debugging Slow You Down! Use Questa One Sim

    Resource (Slides (.PDF)) - Nov 12, 2025 by Nicole Munson

    In this webinar, you will learn how Questa One Sim  empowers VHDL designers to dramatically enhance their debugging productivity.

  • Introducing BUGGED OUT — A new bite-sized podcast for verification engineers

    Resource (Verification Horizons Blog) - Nov 10, 2025 by Harry Foster

    I’m excited to share something I’ve been working on for a while — my new podcast, BUGGED OUT . If you’ve been in verification long enough, you know the truth: Every chip has bugs. The real challenge — and the real creativity — is in how we find and fix them quickly. This podcast is about that work. Each episode is 10–15 minutes, designed for a commute, a coffee break, or that moment when your simulation farm is spinning and you finally have a minute to think.

  • BUGGED OUT Podcast

    Podcast - Nov 10, 2025 by Harry Foster

    Every chip has bugs — the real question is how fast you can find and fix them. BUGGED OUT is the bite-sized podcast where we shine a light on the art (and science) of functional verification.

  • HLV: Formal Verification of Synthesizable C++/SystemC Designs

    Webinar - Nov 05, 2025 by Vlada Kalinic

    Formal check tools are difficult to be analyzed on generated RTL (as the errors cannot be correlated to HLS source code) Catapult Formal/Onespin SystemC help to overcome this challenge. Under HLV there are several apps, to verify and clean C++ HLS code before running HL Synthesis and then apply equivalency between C++ and RTL to guarantee that golden C++ is equivalent with final RTL design.

  • HLV: Formal Verification of Synthesizable C++/SystemC Designs

    Resource (Slides (.PDF)) - Nov 05, 2025 by Vlada Kalinic

    Under HLV there are several apps, to verify and clean C++ HLS code before running HL Synthesis and then apply equivalency between C++ and RTL to guarantee that golden C++ is equivalent with final RTL design.

  • Improving Verification Productivity Using Questa One Sim

    Resource (Slides (.PDF)) - Oct 23, 2025 by Karim Ameziane

    This webinar is essential for verification engineers and managers looking to overcome the challenges of increasing design complexity and achieve superior verification efficiency and faster time-to-market with Siemens' Questa One Sim.

  • Improving Verification Productivity Using Questa One Sim

    Webinar - Oct 23, 2025 by Karim Ameziane

    This webinar is essential for verification engineers and managers looking to overcome the challenges of increasing design complexity and achieve superior verification efficiency and faster time-to-market with Siemens' Questa One Sim. Furthermore, the webinar will showcase Questa One Sim's cutting-edge debugging tools. Experience how advanced capabilities like Protocol Debug, and X-Debug enhance productivity, enabling you to find bugs faster.

  • New RTL Modeling Constructs in Verilog

    Resource (Verification Horizons Blog) - Oct 16, 2025 by Dave Rich

    I’ve been packing up my office as Siemens is closing my location. This marks the longest I’ve ever spent in a single office, a whopping 15 years. Coincidentally, I was in the same building earlier with another company, Avant! for an additional 2 years. I’ve got a box of stuff from previous jobs that I rarely unpack. But it happened to go through it and found the proceedings from what was to become the first DVCon in 1992. I doubt these proceedings exist anywhere in digital form.

  • Combining Performance and Formal Security Guarantees for Hardware Accelerators

    Resource (Slides (.PDF)) - Oct 16, 2025 by Lucas Deutschmann - RPTU University Kaiserslautern-Landau

  • Ground Truth in the Age of AI: Abstract Models as the Anchor of Verification

    Resource (Slides (.PDF)) - Oct 16, 2025 by Tobias Ludwig - Lubis EDA

  • Adaptable FWHW Formal Co-Verification of SoC RISC-V Components

    Resource (Slides (.PDF)) - Oct 16, 2025 by Bryan Olmos - Infineon

    The increasing shift towards the RISC-V open-source instruction set architecture requires the development of new design techniques. In recent years, it has been demonstrated that RISC-V designs can be generated in a modular and scalable manner by utilizing metamodeling techniques.

  • Formally Verifying Security Properties of CHERI Hardware and Software

    Resource (Slides (.PDF)) - Oct 16, 2025 by Thomas Bauereiss - University of Cambridge

  • Harnessing AI for Real-world Hardware Verification

    Resource (Slides (.PDF)) - Oct 16, 2025 by Matthew Taylor - Doulos

  • Stimulus Free Verification of a Clock Bridge Using Static and Formal

    Resource (Slides (.PDF)) - Oct 16, 2025 by Kanthi Palaniappan - Nokia

  • osmosis Europe 2025

    Conference - Oct 16, 2025 by Nicolae Tusinschi

    The osmosis Europe event is a dynamic platform for exchanging successes achieved through applying formal techniques to overcome verification challenges. It offers a unique opportunity to connect and engage with our accomplished research and development (R&D) experts and participants. The conversations that follow may help you and others improve formal-based verification solutions.

  • Ultra Accelerator Link (UALink) Verification: A Deep Dive with Siemens Avery Verification IP

    Webinar - Oct 15, 2025 by Justin Bunnell

    In this webinar, you will be introduced to the UALink protocol, focusing on its architecture, key features that enable scalable AI systems, and critical verification challenges. We will then explore the essential capabilities of Siemens Avery UALink Verification IP, designed to ensure complete and efficient verification of complex UALink-based accelerator designs.

  • Ultra Accelerator Link (UALink) Verification: A Deep Dive with Siemens Avery Verification IP

    Resource (Slides (.PDF)) - Oct 15, 2025 by Justin Bunnell

    In this webinar, you will be introduced to the UALink protocol, focusing on its architecture, key features that enable scalable AI systems, and critical verification challenges.