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AI Assisted FPU Verification Using Questa One SFV

Webinar - Feb 25, 2026 by Gerardo Nahum

One of the key components of the AI revolution is Floating Point Hardware design. Design targeting AI requires at times fast computing with low precision and at times very high precision in its calculations. In this webinar we show how Questa One AI assisted tools for Static Formal, help to generate full formal verification checkers for user defined functionality including floating-point operations.
Verification Academy Live: El Segundo Topgolf

Seminar - Feb 24, 2026 by Joe Hupcey

This seminar explores technologies and techniques you can adopt to increase your verification productivity. We will cover: How the new AI/ML paradigm shift across the industry is enabling functional verification productivity gains Benefits of an automated Continuous Integration flow to enhance RTL quality and streamline development processes Protecting against data corruption with formal security verification Latest advancements in RTL simulation Tuesday, February 24, 2026 | 9:30AM - 5:00PM
Verification Academy Live: Austin Topgolf

Seminar - Feb 19, 2026 by Joe Hupcey

This seminar discusses technologies and techniques you can adopt to increase your verification productivity. We will cover how the new AI/ML paradigm shift across the industry is enabling functional verification productivity gains with Questa One across the verification cycle including RTL creation, simulation, coverage closure, system-level verification and through DFT simulations. Thursday, February 19, 2026 | 9:30 AM - 5:15 PM Location Topgolf 2700 Esperanza Crossing Austin, Texas 78758
Securing Next-Generation Interconnects: PCIe® Gen7 Security Verification

Webinar - Feb 18, 2026 by Jalaj Gupta

This session highlights what’s new in PCIe Gen7 security and demonstrates how Avery Verification IP-built on deep PCIe and UCIe verification expertise-enables early validation of TDISP and IDE functionality, comprehensive protocol and security coverage, and faster compliance, reducing risk and time-to-market for secure PCIe designs.
Don’t Miss CDC Bugs in Low Power Designs!: Formal Meets Power Aware CDC

Resource (Slides (.PDF)) - Feb 11, 2026 by Kurt Takara

In this webinar, you will learn how Questa CDC combines exhaustive formal analysis with automated protocol assertions to prove safe crossings and filter functionally false positives.
Don’t Miss CDC Bugs in Low Power Designs!: Formal Meets Power Aware CDC

Webinar - Feb 11, 2026 by Kurt Takara

This webinar will discuss how Questa CDC Power Aware analysis can address this problem, as well as describe how Questa CDC combines exhaustive formal analysis with automated protocol assertions to prove safe crossings and filter functionally false positives.
Close Coverage Faster with Questa One Sim's Unreachability Analysis

Webinar - Feb 05, 2026 by Justin Royse

Coverage closure remains the single largest challenge facing functional verification teams today, affecting 34% of both ASIC and FPGA design projects. As verification approaches completion, coverage scores plateau well short of project goals—a phenomenon commonly known as the "Last Mile problem." This webinar explores why traditional approaches to closing coverage gaps fall short and introduces  automated unreachability analysis  in Questa One Sim as a transformative solution.
Close Coverage Faster with Questa One Sim's Unreachability Analysis

Resource (Slides (.PDF)) - Feb 05, 2026 by Justin Royse

This webinar explores why traditional approaches to closing coverage gaps fall short and introduces  automated unreachability analysis  in Questa One Sim as a transformative solution.
Compute Subsystem RTL Signoff with CSS VIP and Software Aware VIP

Resource (Slides (.PDF)) - Feb 04, 2026 by Luis Rodriguez

This session highlights a robust methodology to accelerate the development and verification of Compute Subsystems such as Arm® Neoverse™ V3 based and also RISC-V based Compute Subsystem (CSS)-based designs, with a shift-left in simulation and signoff using Avery Protocol VIP, CSS VIP, Software Aware VIP, Arm Fast Models and QEMU models. Guest Presenter: Purna Mohanty – Signature IP
Securing Next-Generation Interconnects: PCIe® Gen7 Security Verification

Resource (Slides (.PDF)) - Feb 04, 2026 by Jalaj Gupta

This session highlights what’s new in PCIe Gen7 security and demonstrates how Avery Verification IP—built on deep PCIe verification expertise—enables early validation of TDISP and IDE functionality, comprehensive protocol and security coverage, and faster compliance, reducing risk and time-to-market for secure PCIe designs.
Verifying Chiplet Interconnects at Scale: UCIe® 3.0

Resource (Slides (.PDF)) - Feb 04, 2026 by Luis Rodriguez

This session highlights what’s new in UCIe 3.0 and explains how Avery UCIe Verification IP enables faster bring-up, deeper protocol coverage, and reduced risk by validating compliance, corner cases, and system-level behavior—helping teams confidently deliver robust chiplet-based silicon. Guest Presenter: Jie Ding – Ayar Labs
Verifying Future Accelerator Interconnects: UALink™ Verification IP and Why UALink Matters

Resource (Slides (.PDF)) - Feb 04, 2026 by Jalaj Gupta

This session highlights the importance of UALink and the verification challenges it introduces and shows how Avery UALink Verification IP delivers immediate value by accelerating bring-up, improving coverage of protocol corner cases, and reducing overall verification risk and time-to-market. Guest Presenter: Saro Kalinagasamy – Astera Labs
Achieving Mathematical Certainty in Design Verification with Formal

Paper - Jan 31, 2026 by Nicolae Tusinschi

This paper provides a comprehensive exploration of formal verification methodologies, techniques, and best practices for hardware design engineers and verification specialists. Formal verification employs mathematical analysis to prove correctness across all possible scenarios. This exhaustive approach is particularly critical in safety-critical systems, high-reliability applications, and complex digital designs where corner-case bugs can have catastrophic consequences.
Achieving Mathematical Certainty in Design Verification with Formal

Resource (Paper (.PDF)) - Jan 31, 2026 by Nicolae Tusinschi

The future of hardware verification lies in the intelligent combination of formal verification, simulation, and other verification methodologies, each applied where it provides the most value. By mastering the techniques presented in this whitepaper, verification engineers position themselves to meet the verification challenges of increasingly complex hardware designs.
Supercharge Your CDC & RDC Analysis with the Power of AI/ML

Webinar - Jan 28, 2026 by Farhad Ahmed

One of the biggest challenges in CDC/RDC verification is managing the complexity and time-consuming nature of identifying and resolving violations. CDC/RDC Assist addresses this challenge by leveraging AI/ML to automate and accelerate causality analysis. In this webinar, you will learn how to streamline CDC/RDC verification using machine learning to automate violation detection and resolution.
Supercharge Your CDC & RDC Analysis with the Power of AI/ML

Resource (Slides (.PDF)) - Jan 28, 2026 by Farhad Ahmed

In this webinar, you will learn how to streamline CDC/RDC verification using machine learning to automate violation detection and resolution.
Simulating CDC Reconvergence: Validating Robustness with Questa One Sim's Metastability Injection

Webinar - Jan 21, 2026 by Sunil Sahoo

This webinar will delve into  Questa One Sim’s groundbreaking metastability injection capability , a pivotal advancement that brings the critical aspect of non-deterministic delay validation directly into the simulation realm. We will demonstrate how this new feature enables designers to actively model and inject varying metastability delays into synchronizer paths, allowing for rigorous verification of sequential reconvergence logic.
Simulating CDC Reconvergence: Validating Robustness with Questa One Sim's Metastability Injection

Resource (Slides (.PDF)) - Jan 21, 2026 by Sunil Sahoo

In this webinar, you will learn how to gain unparalleled confidence in your design’s resilience to metastability effects, ensuring robust functional correctness and accelerating verification closure for complex multi-clock SoCs.
BUGGED OUT Podcast

Podcast - Jan 20, 2026 by Harry Foster

Every chip has bugs — the real question is how fast you can find and fix them. BUGGED OUT is the bite-sized podcast where we shine a light on the art (and science) of functional verification.
New Innovative Way to Functionally Verify Heterogeneous 2D/3D Package Connectivity

Resource (Paper (.PDF)) - Jan 16, 2026 by Jin Hou

The heterogeneous integration of multiple ICs in a single package along with high-performance, high bandwidth memory is critical for many high-performance computing applications. After everything has been heterogeneously integrated and packaged, such designs feature complex connectivity with many hundreds of thousands of connections, making it extremely challenging to verify the correctness of the connections.
New Innovative Way to Functionally Verify Heterogeneous 2D/3D Package Connectivity

Paper - Jan 16, 2026 by Jin Hou

This paper introduces a new way to functionally verify packaging connectivity using formal verification that can exhaustively verify all interconnections between IC blocks. The flow is automatic for all steps, from creating connectivity specifications to verifying packaging output connectivity. The automatic parallel algorithms on the compute grid can verify huge numbers of connections in minutes or even seconds. The script for the flow is simple and only takes a few minutes to set up.
Constrained Randomization and Functional Coverage in Questa One Sim with UVVM

Webinar - Jan 14, 2026 by Abdelrahman Tharwat

In this webinar, we’re excited to showcase the latest cutting-edge features of Questa One Sim, with UVVM (Universal VHDL Verification Methodology) . Learn how the newly added support for constrained randomization with multi-variable capabilities allows you to dynamically generate randomized, UVVM-compliant stimuli that address even the most intricate design constraints, helping you explore vast verification scenarios efficiently and effectively.
Constrained Randomization and Functional Coverage in Questa One Sim with UVVM

Resource (Slides (.PDF)) - Jan 14, 2026 by Abdelrahman Tharwat

This webinar is your gateway to unlocking a streamlined and enhanced verification experience by leveraging Questa One Sim advanced features in tandem with UVVM.
System Verifier

Resource (Verification Horizons Blog) - Jan 05, 2026 by Julie Weber

Software-defined, AI-controlled systems are transforming industries—from aerospace and defense to automotive and industrial automation. But with this transformation comes complexity: as software workloads grow, electronic systems face higher risks of non-deterministic failure mechanisms. Traditional engineering methods and tools are no longer enough to anticipate these risks or prevent “integration hell.”
Formal Verification of Synthesizable C++/SystemC Designs

Resource (Paper (.PDF)) - Dec 12, 2025 by Vlada Kalinic

In this paper, you will learn that HLV formal tools from Siemens can be used to clean SystemC/C++ design code before running HLS as well as to verify the functionality of the SystemC designs with SVA assertions. Steps in this flow include using the GUI counter-example capability to debug failures on the SystemC/C++ designs and focusing on the reachable parts by using the increase coverage solution to detect unreachable code.