Broadcom: Reining in the Complexity of DFT Verification
As semiconductor complexity grows unabated, featuring hundreds of physical core instances and multi-die architectures, validating critical Design for Test (DFT) structures has become exceedingly difficult. The practical size of physical blocks isn't keeping pace with design size, leading to a proliferation of components requiring verification across design generations. This session will introduce techniques and methodologies developed to address these challenges.
