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2017 Results
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Accelerating Functional Coverage with Questa One CX
Webinar - Jun 18, 2025 by Chris Crile
This webinar introduces Questa One Sim CX, an innovative coverage-driven simulation solution that revolutionizes SystemVerilog UVM verification workflows.
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Streamlining Requirements Traceability using Questa Verification IQ Testplan Author
Webinar - May 28, 2025 by Nishtha NLN
In this webinar, discover how Questa Verification IQ Testplan Author seamlessly integrates with Application Lifecycle Management tools (such as Siemens Polarion and Jama Connect) to deliver a powerful, collaborative traceability solution that transforms your verification workflow.
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Solving the Semiconductor Verification Crisis: From Problem to Productivity
Webinar - May 21, 2025 by Harry Foster
In this webinar, you will learn more about the challenges that are currently being faced by the digital design and verification industry and the steps you can take to mitigate some of these challenges.
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A Guide to UPF-based Power Intent Verification with Questa One
Resource (Technical Paper) - May 13, 2025 by Chandu Challapalli
This white paper takes a close look at the verification side of UPF with Questa™ One Sim Power Aware. The focus here is on how to confirm that the described power intent is correctly wired up, tested and functionally sound throughout the design flow.
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Reach the Finish Line Faster: How Questa One Speeds Total Simulation Turnaround Time
Resource (Technical Paper) - May 13, 2025 by Sunil Sahoo
Questa™ One Sim’s SmartCompile emerges as a strategic solution for reducing the overall verification timeline, offering a comprehensive set of tools that substantially reduce the turnaround time from initial compilation to final simulation.
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Raising the Bar in Mission-Critical Verification: Aerospace and Defense Trends Analysis of FPGA Design Practices
Resource (Technical Paper) - May 13, 2025 by Harry Foster
The insights presented in this report serve as a valuable benchmark for A&D organizations aiming to evaluate and enhance their verification maturity, technology adoption, and engineering resource alignment in response to evolving challenges.
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Turning Vision into Reality: How Questa One Fulfills the Promise of Smart Verification
Resource (Technical Paper) - May 13, 2025 by Harry Foster
In this white paper, you will learn how Questa One delivers a next-generation solution engineered to turn verification from a bottleneck into a competitive advantage.
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Questa One Unified Coverage Solution: Transforming Verification Through Intelligence
Resource (Technical Paper) - May 13, 2025 by Vladislav Palfy
This white paper walks through the landscape of semiconductor verification have reached a critical tipping point. What was once manageable through brute force — adding more tests, more compute power, more engineers have become an unsustainable approach.
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Intent Meets Implementation: Verifying Complex Power Strategies with UPF 4.0
Resource (Technical Paper) - May 13, 2025 by Chandu Challapalli
This white paper walks through practical tips and real-world challenges that teams face when rolling out UPF 4.0.
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Accelerated Assurance with Questa One Functional Safety
Resource (Technical Paper) - May 13, 2025 by Jacob Wiltgen
Engineering teams face many challenges in achieving compliance with the ISO 26262 safety standard. To meet these and remain competitive, project teams must innovate and deploy best-in-class tools and workflows.
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A Guide to SDC-based Timing Intent Verification with Questa One
Resource (Technical Paper) - May 13, 2025 by Chandu Challapalli
SDC files play a critical role in defining how a digital design is expected to behave in time. Questa One Sim is an automated and comprehensive solution for SDC verification. It brings structure to SDC verification by combining static analysis, simulation-based checks, and formal validation in one environment.
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Accelerating DFT Sign-Off with Questa One
Resource (Technical Paper) - May 13, 2025 by Jacob Wiltgen
The rapid pace of technological advancement has created an unprecedented demand for highly reliable systems across a wide range of industries. In sectors such as safety critical systems, high-performance computing, and 3DIC, the need for utmost reliability is essential.
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Questa One Smart Verification: Unleashing the Potential of AI in Functional Verification
Resource (Technical Paper) - May 13, 2025 by Darron May
Exploring the potential of AI in verification, this whitepaper delves into the specific challenges the industry faces, showcases innovative solutions being developed, and highlights the successes of early adopters who have embraced these cutting-edge technologies.
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Functional Safety for ISO 26262
Product - May 13, 2025 by Jacob Wiltgen
As electronics become more integrated into daily life, especially in automotive applications, the demand for safer devices has grown. Modern vehicles feature advanced safety systems like lane keep assistance, blind spot detection, and forward collision warnings, with many aiming for Level 3 and 4 autonomy.
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Functional Safety for DO-254
Product - May 13, 2025 by Jacob Wiltgen
DO-254 (Design Assurance Guidance for Airborne Electronic Hardware) is the industry standard for ensuring the safety, reliability, and compliance of airborne electronic hardware. DO-254 defines stringent design assurance requirements for FPGAs and ASICs used in airborne systems. Compliance ensures that these programmable and custom devices meet safety, reliability, and regulatory standards.
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Enhancing Defect Coverage in Design for Testability (DFT) with Functional Fault Grading
Resource (Slides Download) - May 07, 2025 by Ann Keffer
This webinar will offer valuable insights into leveraging functional fault grading for robust and reliable system designs.
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Enhancing Defect Coverage in Design for Testability (DFT) with Functional Fault Grading
Webinar - May 07, 2025 by Ann Keffer
In this webinar, we will explore how functional fault grading enhances defect coverage. Attendees will learn the key advantages of integrating functional fault grading into DFT processes, specifically addressing faults untestable by scan tests.
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Our Journey in Deploying Formal Register Checks with Questa Check Register
Resource (Slides Download) - May 01, 2025 by Thomas Thatcher - Rambus
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Our Journey in Deploying Formal Register Checks with Questa Check Register
Resource (Recording) - May 01, 2025 by Thomas Thatcher - Rambus
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Automated Trust and Assurance for ASIC and FPGA Designs: Mitigating Security Risks with Formal Verification
Resource (Recording) - May 01, 2025 by Mitchell Poplingher
In this presentation, we will introduce Questa Verify Trust and discuss some experiences and initial results from two projects at Lockheed Martin. An objective is to verify the incoming IPs for Trust, as incoming 3rd party RTL IPs may introduce security-relevant weaknesses and vulnerabilities. Another project must complete Trust Verification as a critical step of the Defense Microelectronics Activity (DMEA) trusted flow.
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Automated Trust and Assurance for ASIC and FPGA Designs: Mitigating Security Risks with Formal Verification
Resource (Slides Download) - May 01, 2025 by Mitchell Poplingher
In this presentation, we will introduce Questa Verify Trust and discuss some experiences and initial results from two projects at Lockheed Martin. An objective is to verify the incoming IPs for Trust, as incoming 3rd party RTL IPs may introduce security-relevant weaknesses and vulnerabilities. Another project must complete Trust Verification as a critical step of the Defense Microelectronics Activity (DMEA) trusted flow.
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Tackling Formal Verification of Large Designs using a Modular Approach
Resource (Slides Download) - May 01, 2025 by Ratish Punnoose - Sandia National Laboratories
Performing formal verification of an SoC type design in one go is limited by the tractability of the formal checks as well as by the complexity of writing an assertion that captures the full behavior. We describe approaches to perform verification in a modular way while maintaining assume-guarantee reasoning between the verification units.
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Tackling Formal Verification of Large Designs using a Modular Approach
Resource (Recording) - May 01, 2025 by Ratish Punnoose - Sandia National Laboratories
Performing formal verification of an SoC type design in one go is limited by the tractability of the formal checks as well as by the complexity of writing an assertion that captures the full behavior. We describe approaches to perform verification in a modular way while maintaining assume-guarantee reasoning between the verification units.
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Rapid Retargeting of Formal Connectivity Verification of AI FPGA Systems
Resource (Slides Download) - May 01, 2025 by Benjamin Ting, Linh Nguyen - Microsoft
This presentation describes the development and implementation of a formal-based application flow to successfully address the unique challenges encountered in dynamically retargeting connectivity verification to multiple variants of large-scale, complex FPGA-based, AI-centric cloud hardware designs.
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Rapid Retargeting of Formal Connectivity Verification of AI FPGA Systems
Resource (Recording) - May 01, 2025 by Benjamin Ting, Linh Nguyen - Microsoft
This presentation describes the development and implementation of a formal-based application flow to successfully address the unique challenges encountered in dynamically retargeting connectivity verification to multiple variants of large-scale, complex FPGA-based, AI-centric cloud hardware designs.