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  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages

    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
      • UVM Connect
      • FPGA Verification
      • Coverage

    • Techniques & Tools

      • Verification IQ
      • Verification IP
      • Static-Based Techniques
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • Introduction to UVM
      • UVM Basics
      • Advanced UVM
      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time

    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification

    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

    • UVM Forum

      • Active Questions
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      • UVM Forum

    • SystemVerilog Forum

      • Active Questions
      • Solutions
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      • SystemVerilog Forum

    • Coverage Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
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      • Coverage Forum

    • Additional Forums

      • Announcements
      • Downloads
      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns

    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines

    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Featured & On-Demand

      • Exploring Formal Coverage
      • Processor Customization
      • Interconnect Formal
      • Formal and the Next Normal
      • Formal Verification Made Easy
      • Data Independence and Non-Determinism
      • Exhaustive Scoreboarding
      • Visualizer Debug Environment
      • Webinar Calendar

    • On-Demand Library

      • SystemVerilog Assertions
      • Practical Flows for Continuous Integration
      • Continuous Integration
      • Questa Verification IQ
      • Avery & Siemens VIP
      • Protocol and Memory Interface Verification
      • HPC Protocols & Memories
      • Preparing for PCIe 6.0: Parts I & II
      • High Defect Coverage
      • SoC Design & Functional Safety Flow
      • Complex Safety Architectures
      • All On-Demand Recordings

    • Recording Archive

      • Lint vs Formal AutoCheck
      • FPGA Design Challenges
      • Design Solutions as a Sleep Aid
      • Fix FPGA Failures Faster
      • CDC and RDC Assist
      • The Dog ate my RTL
      • Questa Lint & CDC
      • Hierarchical CDC+RDC
      • Improving Initial RTL Quality
      • CDC Philosophy
      • Hardware Emulation Productivity
      • The Three Pillars of Intent-Focused Insight
      • All Webinar Topics

    • Conferences & WRG

      • 2022 Functional Verification Study
      • Improving Your SystemVerilog & UVM Skills
      • Automotive Functional Safety Forum
      • Aerospace & Defense Tech Day
      • Siemens EDA Functional Verification
      • Industry Data & Surveys
      • DVCon 2023
      • DVCon 2022
      • DVCon 2021
      • Osmosis 2022
      • All Conferences

    • Siemens EDA Learning Center

      • EDA Xcelerator Academy(Learning Services) Verification Training, Badging and Certification
      • View all Xcelerator Academy classes
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

      • Verification IQ
      • Verification Horizons Blog
      • Technical Resources

    • Verification Horizons Publication

      • Verification Horizons - July 2023
      • Verification Horizons - March 2023
      • Verification Horizons - December 2022
      • Issue Archive

    • About Us

      • Verification Academy Overview
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    • Training

      • Learning @OneGlance (PDF)
      • SystemVerilog & UVM Classes
      • Siemens EDA Classes
  • Home
  • Events
  • Aerospace and Defense Verification Tech Day

Aerospace and Defense Verification Tech Day

Join Siemens EDA as we share an engineering update on the methodologies, technologies, and solutions for the ASIC, FPGA, and systems verification challenges unique to today’s aerospace and defense industry. Design and verification engineers and managers serving the aerospace and defense industry won’t want to miss this deep dive into the future of digital verification.

Key topics covered include:

* Model-based systems engineering (MBSE)
* Supply chain resilience
* Trust and security standards
* Developer productivity
* Microelectronics Quantifiable Assurance (MQA)

Rich Powlowsky
Ray Salemi
Russell Klein
Chris Giles
Bob Oden
Joe Hupcey
Rich Edelman
Darron May
John Hallman
Vijay Chobisa
Felipe Schneider
Static-Based Techniques Coverage Debug Formal-Based Techniques Simulation-Based Techniques UVM - Universal Verification Methodology Verification IP
Walk

Sessions

Siemens and the US Government - Mitigating Microelectronics Development Challenges

Siemens: Mitigating Microelectronics Development Challenges | Subject Matter Expert - Rich Powlowsky | Aerospace and Defense Verification Tech Day

Siemens is a full solution provider to the fabless design community, including SoCs and Heterogeneous Integration from concept through GDSII sign off, through to the manufactured wafer and product life cycle. Together with Siemens Govt. Technologies and the broader Siemens portfolio, we offer multi-domain, commercial platforms to the Dept. of Defense community: including secure design, digital engineering and trusted supply chain solutions.

Bringing Model-based Systems Engineering to IC and FPGA Design

Bringing Model-based Systems Engineering to IC and FPGA Design | Subject Matter Expert - Ray Salemi | Aerospace and Defense Verification Tech Day

The Department of Defense has made model-based engineering a requirement for future Aerospace and Defense electronics projects. Ray Salemi will discuss how international competition has forced the change, how model-based design will change the way the Defense Industrial Base works with the DoD, and what all this means for IC verification.

From Model to Implementation with High-Level Synthesis

From Model to Implementation with High-Level Synthesis | Subject Matter Expert - Russell Klein | Aerospace and Defense Verification Tech Day

In an MBSE flow, developers need to make informed choices on the implementation of functions in the system model. This talk will explore how High-Level Synthesis (HLS) can be used to deliver the data needed to make critical design trade-off decisions. We will also cover how HLS can enable system verification in an MBSE flow, and how HLS can mitigate supply chain risks.

Productive Development: Leveraging Early Design Insight to Accelerate Learning Curves and Achieve Program Goals Efficiently

Productive Development: Leveraging Early Design Insight to Accelerate Learning Curves and Achieve Program Goals Efficiently | Subject Matter Expert - Chris Giles | Aerospace and Defense Verification Tech Day

Increasing scope, shrinking schedules and limited resources are challenging Aerospace and Defense projects as never before. You'll learn how Questa Design Solutions accelerates development learning and improves and instruments development efficiency by providing design quality insight early, then monitoring throughout development.

Create a UVM Testbench in a Day Using a Rapid, Repeatable Approach

Create a UVM Testbench in a Day Using a Rapid, Repeatable Approach | Subject Matter Expert - Bob Oden | Aerospace and Defense Verification Tech Day

In this session, you'll learn how the UVM Framework and Questa Verification IP enables testbench creation in a day so the team can focus on creating tests and closing coverage.

How Automation Enables any RTL D&V Engineer to Run Exhaustive Formal Verification

From Zero to Hero: How Automation Enables any RTL D&V Engineer to Run Exhaustive Formal Verification | Subject Matter Expert - Joe Hupcey and David Landoll | Aerospace and Defense Verification Tech Day

In this session, we will start by reviewing the unique capabilities in Siemens EDA's formal solutions, then share a case study on how automated formal "unreachability" analysis can accelerate overall verification coverage closure via integration with QuestaSim. Plus: if you already have some expertise in property checking, we will also share several apps that leverage this experience to address challenges like validating the completeness of your verification plan, processor/RISC-V verification, and FPGA implementation.

Accelerate Development Using Advanced Debugging Approaches

Accelerate Development Using Advanced Debugging Approaches | Subject Matter Expert - Rich Edelman | Aerospace and Defense Verification Tech Day

Visualizer Debug Environment provides a high-performance, high-capacity, tightly integrated debug environment for Simulation and Emulation. Waveform debug and source and connectivity debug for Verilog and VHDL are tightly integrated with class debug and UVM debug, with transaction viewing. Visualizer supports SystemVerilog, SystemC, C++ and C environments in the same way.

Collaborative Verification Management & Coverage Analysis

Collaborative Verification Management & Coverage Analysis | Subject Matter Expert - Darron May | Aerospace and Defense Verification Tech Day

This session will offer an introduction to Siemens next generation Verification Management solution, Verification IQ (VIQ). The session will include an overview of the applications which comprise VIQ, which help manage all verification tasks including test plan creation, coverage analysis, regression management, and metric trending.

Securing the Electronics Development Chain with IC Integrity Solutions

Securing the Electronics Development Chain with IC Integrity Solutions | Subject Matter Expert - John Hallman | Aerospace and Defense Verification Tech Day

In this session we will introduce apps that provide an automated assessment platform, perform processor verification, and offer completeness checking for this very complex IC integrity challenge.

System Level SoC Verification and Validation Using Emulation and Prototype Platforms

System Level SoC Verification and Validation Using Emulation and Prototype Platforms | Subject Matter Expert - Vijay Chobisa | Aerospace and Defense Verification Tech Day

This session covers the Veloce Strato+ emulation platform, delivering fast execution speed, full debug visibility, flexible use models, and ease-of-use in models that span the entire range of needs throughout the life of the chip/SoC development process.

Trust but Verify Your IP with Solido Crosscheck

Trust but Verify Your IP with Solido Crosscheck | Subject Matter Expert - Felipe Schneider | Aerospace and Defense Verification Tech Day

This session will show Solido Crosscheck as the one-stop-shop solution for IP validation and QA accountability among IP designers and IP integrators.

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