Aerospace and Defense Verification Tech Day

Join Siemens EDA as we share an engineering update on the methodologies, technologies, and solutions for the ASIC, FPGA, and systems verification challenges unique to today’s aerospace and defense industry. Design and verification engineers and managers serving the aerospace and defense industry won’t want to miss this deep dive into the future of digital verification.

Functional Safety

Joe Hupcey

Last Updated May 2022

Sessions
- Siemens and the US Government - Mitigating Microelectronics Development Challenges
  
  In this session, you will learn how Siemens is a full solution provider to the fabless design community, including SoCs and Heterogeneous Integration from concept through GDSII sign off, through to the manufactured wafer and product life cycle.
  Track May 10, 2022 by Rich Powlowsky
  
  Functional Safety
- Bringing Model-based Systems Engineering to IC and FPGA Design
  
  In this session, you will learn how international competition has forced the change, how model-based design will change the way the Defense Industrial Base works with the DoD, and what all this means for IC verification.
  Track May 10, 2022 by Ray Salemi
  
  FPGA Verification
- From Model to Implementation with High-Level Synthesis
  
  In this session, you will learn how HLS can enable system verification in an MBSE flow, and how HLS can mitigate supply chain risks.
  Track May 10, 2022 by Russell Klein
  
  High-Level Synthesis
- Accelerate Learning Curves and Achieve Program Goals Efficiently
  
  In this session, you will learn how Questa Design Solutions accelerates development learning and improves and instruments development efficiency by providing design quality insight early, then monitoring throughout development.
  Track May 10, 2022 by Chris Giles
  
  QDS
- Create a UVM Testbench in a Day Using a Rapid, Repeatable Approach
  
  In this session, you'll learn how the UVM Framework and Questa Verification IP enables testbench creation in a day so the team can focus on creating tests and closing coverage.
  Track May 10, 2022 by Bob Oden
  
  UVMF
- How Automation Enables any RTL D&V Engineer to Run Exhaustive Formal Verification
  
  In this session, you will learn about the unique capabilities in Siemens EDA's formal solutions, then share a case study on how automated formal "unreachability" analysis can accelerate overall verification coverage closure via integration with QuestaSim.
  Track May 10, 2022 by Joe Hupcey
  
  Formal Verification
- Accelerate Development Using Advanced Debugging Approaches
  
  In this session, you will learn how Visualizer Debug Environment provides a high-performance, high-capacity, tightly integrated debug environment for Simulation and Emulation.
  Track May 10, 2022 by Rich Edelman
  
  Debug
- Collaborative Verification Management & Coverage Analysis
  
  In this session, you will learn of the applications which comprise VIQ, which help manage all verification tasks including test plan creation, coverage analysis, regression management, and metric trending.
  Track May 10, 2022 by Darron May
  
  Verification Management
- Securing the Electronics Development Chain with IC Integrity Solutions
  
  In this session we will introduce apps that provide an automated assessment platform, perform processor verification, and offer completeness checking for this very complex IC integrity challenge.
  Track May 10, 2022 by John Hallman
  
  Formal Verification
- System Level SoC Verification and Validation Using Emulation and Prototype Platforms
  
  This session covers the Veloce Strato+ emulation platform, delivering fast execution speed, full debug visibility, flexible use models, and ease-of-use in models that span the entire range of needs throughout the life of the chip/SoC development process.
  Track May 10, 2022 by Vijay Chobisa
  
  Acceleration
- Trust but Verify Your IP with Solido Crosscheck
  
  This session will show Solido Crosscheck as the one-stop-shop solution for IP validation and QA accountability among IP designers and IP integrators.
  Track May 10, 2022 by Felipe Schneider
  
  Analog Mixed-Signal
Overview
Join Siemens EDA as we share an engineering update on the methodologies, technologies, and solutions for the ASIC, FPGA, and systems verification challenges unique to today’s aerospace and defense industry. Design and verification engineers and managers serving the aerospace and defense industry won’t want to miss this deep dive into the future of digital verification.
Key topics covered include:
- Model-based systems engineering (MBSE)
- Supply chain resilience
- Trust and security standards
- Developer productivity
- Microelectronics Quantifiable Assurance (MQA)