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UVM Testbench Structure and Coverage Improvement in a Mixed Signal Verification Environment
Article - Jun 16, 2014 by Mihajlo Katona - Veriest
This article discusses how a UVM verification environment was set up easily for a mixed signal device under test (DUT) using a scripting tool developed in-house and based on a testbench configuration file. The article focuses mostly on presenting two mixed signal DUT examples and the corresponding UVM-based testbench with a digital-ontop structure.
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UVM 1.2 Class Reference
Resource (Reference Documentation) - Jun 13, 2014 by
v1.2 The UVM Class Library provides the building blocks needed to quickly develop well-constructed and reusable verification components and test environments in SystemVerilog. This UVM Class Reference provides detailed reference information for each user-visible class in the UVM library. For additional information on using UVM, see the UVM User’s Guide located in the top level directory within the UVM kit.
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UVM 1.2 is Coming: So Be Prepared
Webinar - May 15, 2014 by Tom Fitzpatrick
In this session, you will learn everything you need to know about the future of UVM including new features, performance, backward-compatibility concerns and more.
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Verification Cookbook Glossary
Chapter - Mar 31, 2014 by Verification Methodology Team
This page is an index to the glossary of various terms defined and used in the Cookbook.
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Sequence Library
Chapter - Mar 31, 2014 by Verification Methodology Team
Updating your VIP/testbench sequence library is one task that you may have to perform while migrating from OVM to UVM.
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Convert Phase Methods
Chapter - Mar 31, 2014 by Verification Methodology Team
Part of the OVM to UVM conversion process is to change the method names for OVM phase methods (build, connect, run, etc) to the new UVM signature for phase methods.
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Migrating from OVM to UVM
Chapter - Mar 31, 2014 by Verification Methodology Team
A Roadmap for upgrading to UVM - this guide covers the minimum steps to upgrade your VIP and testbench from OVM to UVM compatibility, then goes into more detail on some further steps for UVM conformance.
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Questa Compiling UVM
Chapter - Mar 31, 2014 by Verification Methodology Team
The UVM class library is an open source SystemVerilog package that relies on DPI c code in order to implement some of the library features such as regular expression matching and register backdoor accesses.
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Deprecated Code
Chapter - Mar 31, 2014 by Verification Methodology Team
Accellera UVM1.0 used OVM2.1.1 as it's basis, with the intention of preserving backwards compatibility where possible.
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Phase Aware
Chapter - Mar 31, 2014 by Verification Methodology Team
OVM code can be ported to run on the UVM.
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Arbitrating Between Sequences
Chapter - Mar 31, 2014 by Verification Methodology Team
The uvm_sequencer has a built-in mechanism to arbitrate between sequences which could be running concurrently on a sequencer.
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UVM Configuration Database
Chapter - Mar 31, 2014 by VM Team
The UVM_config_db class is the recommended way to access the resource database. A resource is any piece of information that is shared between two or more components or objects. Use UVM_config_db::set to put information into the database and use UVM_config_db::get to retrieve information from the database. The UVM_config_db class is a type-parameterized class, and consequently the database behaves as if it were partitioned into many type-specific "mini databases."
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Sequence API
Chapter - Mar 31, 2014 by Verification Methodology Team
A uvm_sequence is derived from an uvm_sequence_item and it is parameterized with the type of sequence_item that it will send to a driver via a sequencer.
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Reporting Verbosity
Chapter - Mar 31, 2014 by Verification Methodology Team
UVM provides a built-in mechanism to control how many messages are printed in a UVM based testbench. This mechanism is based on comparing integer values specified when creating a debug message using either the uvm_report_info() function or the `uvm_info() macro.
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Built in Debug
Chapter - Mar 31, 2014 by Verification Methodology Team
Learn about various debug techniques and support for SystemVerilog and UVM with features supplied with the UVM to assist in common problem debug.
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Matlab Integration
Chapter - Mar 31, 2014 by Verification Methodology Team
MATLAB is a modeling tool often used to develop functional models of complex mathematical functions which will then be translated into RTL library blocks.
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UVM Phasing
Chapter - Mar 31, 2014 by Verification Methodology Team
Phasing is a stepwise construction approach of a verification environment at runtime and the execution of required stimulus and completion of the test. UVM has an API enabling components to participate in this step by step process. The construction of structured test environments with TLM connections is done in a predetermined manner to enable smart hierarchy and connectivity management. Most verification environments use the simplest possible subset of the available phases: build, connect, run.
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Accessing Configuration Resources from a Sequence
Chapter - Mar 31, 2014 by Verification Methodology Team
Sequences often need access to testbench resources such as register models or configuration objects.
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Testbench Configuration
Chapter - Mar 31, 2014 by Verification Methodology Team
One of the key tenets of designing reusable testbenches is to make testbenches as configurable as possible. Doing this means that the testbench and its constituent parts can easily be reused and quickly modified (i.e. reconfigured).
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UVM Packages
Chapter - Mar 31, 2014 by VM Team
A package is a SystemVerilog language construct that enables related declarations and definitions to be grouped together in a package namespace. A package might contain type definitions, constant declarations, functions and class templates. To use a package within a scope, it must be imported, after which its contents can be referenced.
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Dual Top Architecture
Chapter - Mar 31, 2014 by VM Team
The dual top testbench architecture advocated throughout this cookbook enables platform portability - it is fundamental for testbench acceleration using emulation or some other hardware-assisted platform. The HDL top level module encapsulates everything associated directly with the clock cycle-based signal level activity of the RTL DUT, which can be run in simulation or be mapped (i.e. synthesized) onto the emulator.
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Parameterized Tests
Chapter - Mar 31, 2014 by VM Team
SystemVerilog provides a number of ways to pass changeable values through different code structures. Some changeable values must be fixed at elaboration time, others can be changed at run-time after starting a simulation. Changeable values fixed at elaboration time are represented using either a SystemVerilog parameter or `define macro. The use of `define macros causes complications in cases of multiple instances of a module or interface where each instance needs a different changeable value.
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Testbench Build
Chapter - Mar 31, 2014 by VM Team
The first phase of a UVM testbench is the build phase. During this phase, the uvm_component classes that make up the testbench hierarchy are constructed into objects. The construction process works top-down with each level of the hierarchy constructed and configured before the next level down (sometimes also referred to as deferred construction).
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Configuring Sequences
Chapter - Mar 31, 2014 by Verification Methodology Team
A frequently encountered scenario in sequence configuration involves setting up the agent's configuration object, encompassing its constituent components such as the sequencer, driver, monitor, and more.
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UVM Agent
Chapter - Mar 31, 2014 by Verification Methodology Team
A UVM agent is a verification component "kit" for a given logical interface such as APB or USB. The agent includes a SystemVerilog interface encapsulating the corresponding set of interface signals, two SystemVerilog interfaces representing the monitor and driver BFMs, and a SystemVerilog package including the various classes that make up the overall agent class component.