Controlling On-the-Fly-Resets in a UVM-Based AXI Testbench
Despite being a common requirement, handling hardware resets in a verification environment has always been beset by a host of challenges, including:
Despite being a common requirement, handling hardware resets in a verification environment has always been beset by a host of challenges, including:
- Reset behavior has to be propagated to all testbench components.
- All UVM components such as driver monitor and scoreboard should be capable of reacting to the reset (i.e., they should be made reset aware).
- All pending sequences already scheduled by the test should be removed from all sequencers and virtual sequencers.
- Once the system comes out of reset the traffic should be re-generated to the DUT.
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