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Façade

Resource (Pattern) - Dec 18, 2015 Harry Foster

A façade pattern provides a simple interface to a complex system, making it easier for the client or external world to use.
BFM-Proxy Pair

Resource (Pattern) - Dec 18, 2015 Harry Foster

The BFM-Proxy Pair Pattern is an Environment Pattern to facilitate the design of transactors like drivers and monitors for dual domain partitioned testbenches that can be used for both simulation and emulation, and across verification engines (or platforms) in general.
Extending a Traditional VIP to Solve PHY Verification Challenges

Resource (Paper (.PDF)) - Dec 10, 2015 Amit Tanwar

In this paper, you will learn that PHY verification requires additional focus because various subtleties required for a comprehensive PHY verification tend to be ignored by a traditional VIP solution.
Extending a Traditional VIP to Solve PHY Verification Challenges

Paper - Dec 10, 2015 Amit Tanwar

A comprehensive PHY verification plan must verify all of the PHY functionality in various conditions. Verification IP needs to serve hundreds of configurations and may not fit well for comprehensive PHY verification. A PCI Express Verification IP in itself covers more than 500 configurations. This creates the need of an extended version of Verification IP which completely focus on PHY related aspects.
Verification IP Stimulus APIs: Are They Really Easy to Use?

Paper - Dec 01, 2015 Amit Kumar Jain - Siemens EDA

With the increasing complexity of system designs, there is a pressing need for standalone, pre-verified, built-in verification infrastructures. Verification IP (VIP) is an integral and important component of these infrastructures for block and system-level verification as they reduce cycles spent in verifying complex designs.ly Easy to Use?
Verification IP Stimulus APIs: Are They Really Easy to Use?

Resource (Paper (.PDF)) - Dec 01, 2015 Amit Kumar Jain - Siemens EDA

Stimulus generation is an important aspect of verification for creating both simple and complex scenarios used to hit functional bugs in a design. Stimulus generation application program interfaces (API) in VIP help you write stimulus without much protocol knowledge and help them create complex protocol scenarios for testing.
Patterns Library

Pattern - Dec 01, 2015 Harry Foster

The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).
UVM Framework: Create a UVM Environment in Less than an Hour

Webinar - Nov 25, 2015 Bob Oden

In this session you will learn how the UVM Framework delivers reuse from block to chip to system in simulation and emulation and how to reduce your verification schedule by at least four weeks on every project.
UVM Framework: Create a UVM Environment in Less than an Hour

Resource (Slides (.PDF)) - Nov 25, 2015 Bob Oden

In this session you will learn how the UVM Framework delivers reuse from block to chip to system in simulation and emulation and how to reduce your verification schedule by at least four weeks on every project.
Leveraging Verification IP (VIP) for Fast & Efficient Verification

Resource (Slides (.PDF)) - Nov 25, 2015 Jason Polychronopoulos

In this session you will learn how Verification IP (VIP) helps to overcome IP verification challenges.
Leveraging Verification IP (VIP) for Fast & Efficient Verification

Webinar - Nov 25, 2015 Jason Polychronopoulos

In this session you will learn how Verification IP (VIP) helps to overcome IP verification challenges.
Technical Paper: A New Stimulus Model for CPU Instruction Sets

Resource - Nov 24, 2015
UVM Forum - All Slides

Resource (Slides (.PDF)) - Nov 24, 2015
UVM Forum Seminar - 2015: UVM Enabled Advanced Storage IP Silicon Success

Resource - Nov 24, 2015
UVM and Emulation - Easing the Path to Advanced Verification and Analysi

Resource (Slides (.PDF)) - Nov 24, 2015 Sanjay Gupta
Automating Scenario-Level UVM Tests with Portable Stimulus

Resource (Slides (.PDF)) - Nov 24, 2015 Matthew Ballance

In this session, you will learn how to easily leverage lower-level descriptions, such as sequence items, in larger scenarios and efficiently and predictably exercise the scenario space, ensuring high quality verification results.
UVM Forum Seminar - 2015: Improving UVM Testbench Debug Productivity and Visibility

Resource - Nov 24, 2015
Creating UVM Testbenches for Simulation & Emulation Platform Portability

Resource (Slides (.PDF)) - Nov 24, 2015 Hans Van Der Schoot

In this session, you will learn the fundamentals of hardware-assisted testbench acceleration.
UVM Forum Seminar - 2015: UVM Technology Overview

Resource - Nov 24, 2015
UVM Forum Seminar - 2015: UVM Everywhere: Industry Drivers, Best Practices, and Solutions

Resource - Nov 24, 2015
ISO 26262 Fault Analysis – Worst Case is Really the Worst

Article - Nov 10, 2015 Avidan Efody

Imagine you’re a verification engineer being asked to get a small 10K gate design ISO 26262 certified. Assuming you don’t take the smart decision to quit your job, what would be your first step? If you would have been asked to do plain functional verification of the design, it is obvious you would start by reading the DUT spec.
Memories Are Made Like This

Article - Nov 01, 2015 Mark Peryer

One of the most common requirements for the verification of a chip, board or system is to be able to model the behavior of memory components, and this is why memory models are one of the most prevalent types of Verification IP (VIP).
A New Stimulus Model for CPU Instruction Sets

Article - Nov 01, 2015 Staffan Berg, Mike Andrews - Siemens EDA

Verifying that a specific implementation of a processor is fully compliant with the specification is a difficult task. Due to the very large total stimuli space it is difficult, if not impossible, to ensure that every architectural and micro-architectural feature has been exercised. Typical approaches involve collecting large test-suites of real SW, as well as using program generators based on constrained- random generation of instruction streams, but there are drawbacks to each.
On-Chip Debug – Reducing Overall ASIC Development Schedule Risk

Article - Nov 01, 2015 Eric Rentschler - Siemens EDA

With ASIC complexity on the increase and unrelenting time-to-market pressure, many silicon design teams still face serious schedule risk from unplanned spins and long post-silicon debug cycles. However, there are opportunities on both the pre-silicon and post-silicon sides that can be systematically improved using on-chip debug solutions.
Hardware Emulation: Three Decades of Evolution - Part III

Article - Nov 01, 2015 Dr. Lauro Rizzatti - Rizzatti LLC

At the beginning of the third decade, circa 2005, system and chip engineers were developing evermore complex designs that mixed many interconnected blocks, embedded multicore processors, digital signal processors (DSPs) and a plethora of peripherals, supported by large memories. The combination of all of these components gave real meaning to the designation system on chip (SoC).