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PSS (38)
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Scoreboard (36)
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PCIe (34)
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Abstraction (33)
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Classes (33)
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Non-Trivial Bug Escapes (33)
Project Time (33)
ASIC (32)
CDC Methodology (32)
DFT (32)
Reset Issues (32)
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Waveform (32)
Block Level (31)
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Properties (31)
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DO-254 (30)
Patterns (30)
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System Level (30)
Test Planning (30)
osmosis 2022 (30)
Accellera (29)
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Chiplets (29)
FSM (29)
Lint (29)
Verilog (29)
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PCI Express (28)
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Signal (28)
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Verification Effectiveness (28)
Assurance (27)
Introduction to UVM (27)
Packages (27)
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Synchronization (27)
Acceleration (26)
Config_db (26)
Design for Test (26)
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U2U (26)
VRM (26)
Archive (25)
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Netlist (25)
Object Oriented Programming (25)
User2User (25)
BFMs (24)
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Memory (24)
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Strategy (24)
UVM Basics (24)
Arrays (23)
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Test Plan (23)
U2U Europe (23)
Validation (23)
Verification Effort (23)
osmosis 2024 (23)
C (22)
Constrained Random Verification (22)
Fault Injection (22)
Gate-Level (22)
Interrupts (22)
Monitors (22)
Power Intent (22)
Proofs (22)
Sequence Item (22)
Sequencer (22)
Automation (21)
Big Data (21)
CDC Analysis (21)
Constrained Random Stimulus (21)
Livesim (21)
Multi-Die (21)
Python (21)
osmosis 2023 (21)
2022 Study (20)
Advanced UVM (20)
Agent (20)
Analog (20)
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Controllers (20)
Data Types (20)
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Reporting (20)
SLEC (20)
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Stimulus Generation (20)
Sub-system (20)
Testplan (20)
UCIe (20)
Universal Chiplet Interconnect Express (20)
Verification Architecture (20)
Verification Practice (20)
Verification Run Manager (20)
Virtual Sequences (20)
X-Tracing (20)
2026 Study (19)
API (19)
Agentic Workflow (19)
Coverage Points (19)
Macros (19)
Requirements Management (19)
Scenario Generation (19)
Static & Formal Adoption (19)
Testbench Automation (19)
2020 Study (18)
Advanced Debug Techniques (18)
Code Generator (18)
Convergence (18)
Fault Grading (18)
Fault Simulation (18)
HLS (18)
IC Reliability (18)
Interconnect (18)
Re-spins (18)
Sequence Driver (18)
State Space (18)
Traceability (18)
Configuration Object (17)
Connections (17)
Data Management (17)
Data Models (17)
Electronic Systems (17)
Object-Oriented Programming in SystemVerilog (17)
Productivity Gap (17)
Prototyping (17)
Randomization (17)
Variable (17)
2014 Study (16)
2018 Study (16)
ABV (16)
AXI (16)
Assertion-Based Verification (16)
Expressions (16)
Failure Analysis (16)
Gate-Level Simulation (16)
Intelligent Automation (16)
Reset-Domain Checking (16)
X-Propagation (16)
2016 Study (15)
AMBA (15)
Class Objects (15)
Continuous Integration System (15)
DPI-C (15)
Declaration (15)
Generation (15)
HDL (15)
Hierarchical Components (15)
Implementation Model (15)
Inconclusives (15)
Parameterized Classes (15)
QVIP Configurator (15)
RDC Analysis (15)
SVA (15)
Timing (15)
osmosis Europe 2025 (15)
3DIC (14)
Automotive Functional Safety Forum (14)
COCOTB (14)
Checkers (14)
Customization (14)
Design Flow (14)
Embedded Processor Cores (14)
FPU (14)
Formal Application (14)
Handles (14)
Hardware Acceleration (14)
High Speed (14)
Jenkins (14)
March 2016 - Volume 12 Issue 1 (14)
NVMe (14)
Operators (14)
Overrides (14)
Parameter (14)
Reachability Checks (14)
Register Layer Adapter (14)
Root Cause (14)
UCDB (14)
UVMC Kit (14)
Unified Power Format (14)
Breakpoint (13)
Class Handles (13)
Co-Simulation (13)
Cross Coverage (13)
Data Mining (13)
First-Silicon Success (13)
Functional Correctness (13)
Glitches (13)
Iterations (13)
Methods (13)
Modules (13)
Power Optimization (13)
Python for Verification Series (13)
RTL Sign-Off (13)
Scalable Verification (13)
Testbench Architecture (13)
VIQ (13)
Verification IQ (13)
ASIL (12)
ATPG (12)
DVCon Japan (12)
Deadlock (12)
Digital Design (12)
Environment Pattern (12)
HPC (12)
Memory Models (12)
Predictive Analysis (12)
RDC Design (12)
Runtime (12)
September 2021 - Volume 17 Issue 2 (12)
Specification (12)
Unit Testing (12)
Verification Component (12)
Verification Maturity (12)
AI-Assisted (11)
Aerospace and Defense Verification Tech Day (11)
Bitstream (11)
C++ (11)
Creating and Using Constrained Random (11)
DAC 2019 (11)
DFT Methodology (11)
Diagnostic Coverage (11)
FMEDA (11)
Fault Analysis (11)
Formal Assertion-Based Verification (11)
Formal Verification Apps (11)
Inheritance (11)
Interview (11)
Isolation (11)
June 2015 - Volume 11 Issue 2 (11)
June 2017 - Volume 13 Issue 2 (11)
Messaging (11)
Metastable (11)
Model Checking (11)
OVM (11)
PYUVM (11)
Pipelined (11)
Processor Design Verification (11)
Property Debug (11)
RDC Methodology (11)
Reference Model (11)
Register Package (11)
Reset Architecture (11)
Root of Trust (11)
SPI (11)
Safety Metrics (11)
TLM FIFOS (11)
Test Environment (11)
Time-to-Market (11)
Tool Assessment (11)
Transaction-Level (11)
Verification Process Overview (11)
Agentic AI Framework (10)
Backdoor Accesses (10)
Bins (10)
Bug Detection (10)
CDC Path (10)
Class Reference (10)
Clock Gating (10)
Command API (10)
Corner-case Bugs (10)
Encapsulation (10)
Floating-Point Units (10)
High-Level Synthesis (10)
July 2022 - Volume 18 Issue 2 (10)
June 2013 - Volume 9 Issue 2 (10)
LLMs (10)
MBIST (10)
Matlab (10)
Metrics-Driven (10)
Parallel Simulation (10)
Proof Coverage (10)
RDC Violations (10)
Respins (10)
Safety (10)
Safety Verification (10)
Software-Driven Verification (10)
Spice (10)
State Transitions (10)
Supply Set (10)
Test Class (10)
Test Generation (10)
Transaction Recording (10)
UALink (10)
Waivers (10)
X-Checking (10)
X-Corruption (10)
osmosis 2025 (10)
1800.2 (9)
AI Algorithms (9)
AI Model (9)
Autonomous Systems (9)
B/C/R Script (9)
Bus Protocol (9)
CDC Protocol (9)
Conditionals (9)
Conversion (9)
Coverage Measurement (9)
Creating and Using Functional Coverage (9)
Curriculum (9)
DDR (9)
Data Types and Procedural Statements (9)
Digital Twin (9)
Ethernet (9)
HDL Domain (9)
Hardware Security (9)
Hierarchical Flow (9)
Hierarchical Sequences (9)
June 2012 - Volume 8 Issue 2 (9)
June 2014 - Volume 10 Issue 2 (9)
June 2018 - Volume 14 Issue 2 (9)
Learning Paths (9)
Multi-Core Architectures (9)
PSL (9)
Phasing (9)
Pin Level (9)
Power Analysis (9)
Power Logic (9)
Reconvergence (9)
Reset Tree (9)
Retention (9)
Schematic (9)
Schematic Debug (9)
Secure Data Path (9)
Sequence-Driver Use Models (9)
Siemens Xcelerator Academy (9)
Skill Building (9)
Static Checks (9)
Sub-system Level (9)
System Scaling (9)
Testing Strategies (9)
Threads (9)
Training (9)
UCIe 3.0 (9)
UVM Stimulus, Tests, and Regressions (9)
Use Models (9)
VHDL 2008 (9)
Verification Complete (9)
Whats New in Functional Verification (9)
APB (8)
Algorithms (8)
Behavioral Modeling (8)
Bus Functional Models (8)
Cache Coherency (8)
Callbacks (8)
Computational Storage (8)
Compute Subsystems (8)
Context-Aware Debug (8)
Coverage Goals (8)
DMA Engine (8)
Design and Verification IP Forum (8)
Directed Test (8)
Error Traces (8)
Factory Pattern (8)
February 2013 - Volume 9 Issue 1 (8)
Guidelines (8)
HTML Docs (8)
Integration Level (8)
June 2016 - Volume 12 Issue 2 (8)
March 2021 - Volume 17 Issue 1 (8)
NVM Express (8)
OSCI (8)
OVM2UVM (8)
Objections (8)
Occurrence Property Pattern (8)
PHY (8)
Postsim (8)
Procedural Statements (8)
Release (8)
Simulation Coverage (8)
Slave (8)
State Machine (8)
Structural Analysis (8)
Technology Scaling (8)
Test Verification (8)
UCIe 2.0 (8)
UVM Verification (8)
Verification Models (8)
Voltage Domain Crossing (8)
Windows (8)
Wishbone (8)
XML (8)
osmosis 2023 A&D (8)
ADAS (7)
Adaptive (7)
Artificial Neural Network (7)
BISR (7)
Base Class (7)
Bind (7)
Black Boxing (7)
Bounded Proof (7)
Build Phase (7)
Class Types (7)
Clocking Verification Challenges (7)
Connecting the Testbench to the Design (7)
Converters (7)
Data Transfer (7)
Design Completion (7)
Design Constraints (7)
Design Hierarchy (7)
Design IP (7)
Design Integrity (7)
Error Injection (7)
Execution Semantics and Synchronization (7)
Fabric (7)
Flip-Flop (7)
Fork-Join (7)
Formal Methods (7)
Front and Back Door (7)
GPU (7)
IP Integration (7)
IP Security (7)
ISA (7)
Instance (7)
Israel Static & Formal Tech Day (7)
July 2020 - Volume 16 Issue 2 (7)
Layering (7)
MCPs (7)
March 2015 - Volume 11 Issue 1 (7)
March 2022 - Volume 18 Issue 1 (7)
March 2023 - Volume 19 Issue 1 (7)
Migration (7)
Non-Determinism (7)
November 2014 - Volume 10 Issue 3 (7)
November 2015 - Volume 11 Issue 3 (7)
Order Property Pattern (7)
Parameterized Tests (7)
Post-silicon Debug (7)
Power Estimation (7)
Predictors (7)
Property Analysis (7)
QEMU (7)
Report (7)
Sequential Analysis (7)
Siemens EDA (7)
Supply Network (7)
Syntax (7)
Testbench Customization in UVM (7)
Tool Qualification (7)
UVVM (7)
Unified Coverage Database (7)
VA Live 2023 - Huntsville (7)
Verbosity (7)
Verification Quality (7)
Verification Workflow (7)
X-Effects (7)
AEH (6)
Address Mapping (6)
Appendix (6)
Bandwidth (6)
Bugged Out Podcast (6)
Clock Propagation (6)
Co-Verification (6)
Concurrent Processes (6)
Coverage Holes (6)
Coverage Intent (6)
Coverpoint (6)
Creating and Using a Test Plan (6)
DAC 2018 (6)
Data Link (6)
December 2017 - Volume 13 Issue 3 (6)
December 2022 - Volume 18 Issue 3 (6)
Defect Coverage (6)
Design Assurance (6)
Design Mitigation (6)
Design Patterns (6)
Design Scaling (6)
Development Environment (6)
Distributed Resource Management (6)
Dual Domains (6)
Dynamic Power (6)
Electronic Hardware (6)
FIT Rate (6)
HDM (6)
HVL (6)
Hardware Designs (6)
Hardware-Assisted Verification (6)
Hierarchical Data Model (6)
IC Design (6)
Implicit/Explicit (6)
June 2019 - Volume 15 Issue 2 (6)
MARLUG 2023 (6)
MIPI (6)
March 2014 - Volume 10 Issue 1 (6)
March 2017 - Volume 13 Issue 1 (6)
March 2020 - Volume 16 Issue 1 (6)
March 2024 - Volume 20 Issue 1 (6)
Metric Validation (6)
November 2016 - Volume 12 Issue 3 (6)
November 2020 - Volume 16 Issue 3 (6)
October 2012 - Volume 8 Issue 3 (6)
October 2013 - Volume 9 Issue 3 (6)
Open Source (6)
PCIe Gen 7 (6)
PCIe Gen 8 (6)
Phases (6)
Power Efficiency (6)
Pre-Silicon (6)
Precedence (6)
Random Faults (6)
Register Checks (6)
Reset Handling (6)
Semiconductor (6)
Sequence Library (6)
Silicon Lifecycle Management (6)
Split Transactor (6)
Static Analyses (6)
Static RDC (6)
Stimulus Free Verification (6)
Tessent Test Solutions (6)
Transactors (6)
USB (6)
UVM Forum (6)
UVM Monitor (6)
VA Live 2024 - El Segundo (6)
VA Live 2024 - San Diego (6)
VA Live 2025 - El Segundo (6)
VA Live 2025 - Hudson (6)
VA Live 2025 - Huntsville (6)
VA Live 2026 - Hudson (6)
VHDL Testbench (6)
Verification Bottleneck (6)
Verification Cycles (6)
Virtual Prototyping (6)
Visualization (6)
YAML (6)
osmosis 2024 A&D (6)
Advance Your Verification Methodology (5)
Agile Development (5)
Analysis Pattern (5)
Analysis Port (5)
Application Lifecycle Management (5)
Arbitration (5)
Argument (5)
Autonomous Vehicles (5)
BIST (5)
Bidirectional (5)
Bounded Tasks (5)
CHERI (5)
CXL (5)
Checkpoint (5)
Class Library (5)
Constraint Solver (5)
Control Logic (5)
DAC 2024 (5)
DSP (5)
Data Encryption (5)
Debug Challenges (5)
December 2019 - Volume 15 Issue 3 (5)
Design Creation (5)
Design Cycle (5)
Design for Safety (5)
Domain Specific Architectures (5)
Driver Tracing (5)
Dual Top (5)
Error (5)
Exhaustive (5)
February 2019 - Volume 15 Issue 1 (5)
Formal Testbench (5)
Function (5)
HBM (5)
HBM4 (5)
Hardware Verification (5)
IDE (5)
IP Blocks (5)
In-Circuit Emulation (5)
In-System Test (5)
JEDEC (5)
LRM (5)
Low Latency (5)
Low Power Verification Forum (5)
MARLUG 2024 (5)
MARLUG 2025 (5)
March 2018 - Volume 14 Issue 1 (5)
Memory Usage (5)
Memory-Mapped Registers (5)
Metastability Injection (5)
Model Context Protocol (5)
Multi-Language Environment (5)
Namespaces (5)
Non-Pipelined (5)
Non-Reset (5)
Partitioning (5)
Processor Core Verification (5)
Quirky (5)
RTL Model (5)
Repository (5)
Reset Signal (5)
SFV (5)
SSD (5)
SVTB (5)
SVUnit (5)
Semantics (5)
Sequential Optimization (5)
Serial Interface (5)
Shift Left (5)
Simulink (5)
State-Based Model (5)
Stimulus Pattern (5)
Test Coverage (5)
Transaction-Based Acceleration (5)
UART (5)
UVC (5)
Unreachability (5)
VA Live 2019 - Westford (5)
VA Live 2023 - Westford (5)
VA Live 2024 - Huntsville (5)
VA Live 2024 - Westford (5)
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VA Live 2026 - El Segundo (5)
Verbose (5)
Verification Case Document (5)
Verification Success (5)
Virtual Methods (5)
X-Aware (5)
X-Mitigation (5)
5G (4)
AHB (4)
AI Agents (4)
AMS Engines (4)
AMS Simulation (4)
Architectural Verification (4)
Batch and Debug (4)
Bi-Directional (4)
Bias (4)
Bit Width (4)
Boolean (4)
Boundary Elements (4)
Bounded Model Checking (4)
CDC Violations (4)
CPU Model (4)
Case Statements (4)
Class Variables (4)
Classifications (4)
Cone of Influence (4)
Coverage Achievement (4)
DVFS (4)
Data Processing (4)
Deprecated (4)
Design Analysis (4)
Design Specification (4)
Determinism (4)
Digital Domain (4)
DisplayPort (4)
Domain Configuration (4)
ECO (4)
ED-80 (4)
ENV Package (4)
Enumeration (4)
Equivalence Validation (4)
Equivalent RTL (4)
Fault Coverage (4)
Fault Detection (4)
Fault List (4)
Fibre Channel (4)
Firmware (4)
Formal Closure (4)
Formal Models (4)
HDMI (4)
Hybrid Virtual Platform (4)
ICE Mode (4)
IEEE (4)
Implementation Driven Formal (4)
Implementation Pattern (4)
In-Circuit Simulation (4)
Initial States (4)
Instantiate (4)
LFM (4)
Language Constructs (4)
Large Language Models (4)
MARLUG 2026 (4)
Mathworks (4)
Mitigation Architecture (4)
November 2018 - Volume 14 Issue 3 (4)
Objectives (4)
PCIe Gen 6 (4)
Packet Transfer (4)
Parallel Compile (4)
Phase Objections (4)
Pipe Interface (4)
Plusargs (4)
Power Constraints (4)
Protocol Checkers (4)
Proxy Class (4)
QoR (4)
Questa Design Solutions (4)
RTL Verification (4)
RTL-Aware Design (4)
Race Conditions (4)
Reconfiguration (4)
Register-Level Scoreboards (4)
Resource Utilization (4)
Retargeting Flow (4)
Risk Mitigation (4)
Sequential Logic (4)
Software Aware (4)
Specification Pattern (4)
Static Analysis (4)
Static Timing (4)
Stream (4)
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Subscriber (4)
Synchronizer (4)
Synergistic Verification (4)
Synthesizable (4)
Tcl/Tk (4)
Test Ranking (4)
Time Cone (4)
Tool Optimization (4)
Toolkit (4)
Top Down (4)
Trust Verification (4)
UCIS (4)
UEC (4)
UPF 3.0 (4)
UPF 4.0 (4)
UVM 1.1d (4)
UVM 1.2 (4)
Unidirectional (4)
VA Live 2023 - Austin (4)
VA Live 2024 - Austin (4)
VA Live 2024 - Fremont (4)
VA Live 2025 - Scottsdale (4)
VA Live 2026 - Austin (4)
VA Live 2026 - Silicon Valley (4)
VPM (4)
Vectors (4)
Verification Blueprint (4)
Virtual Sequencers (4)
Wave Window (4)
$display (3)
1.2 (3)
AMS Verification (3)
APB3 (3)
Abstract Class (3)
Abstract-Concrete (3)
Access Path (3)
Affect Probability (3)
Airborne Electronic Hardware (3)
Analysis Components (3)
Base Test (3)
BiQuad (3)
Bidirectional Protocols (3)
Block Diagram (3)
Build Process (3)
Built-In Self-Test (3)
CDC Signals (3)
CSI-2 (3)
Cause-Effect (3)
Certification (3)
Clock Definitions (3)
Clock Detection (3)
Clocking (3)
Code Quality (3)
Command Line Processor (3)
Connect Phase (3)
Controllability (3)
Coroutines (3)
Cover Method (3)
Coverage Data (3)
Coverage Exclusion (3)
Coverage-Driven Verification (3)
Critical Storage (3)
Cross-Domain (3)
Cryptography (3)
Cutpoint (3)
DFT Architecture (3)
Delay Loops (3)
Design Under Test (3)
Designers (3)
Domain Topologies (3)
ESL (3)
Emulatability (3)
FWHW (3)
Fault Model (3)
Finite State Machine (3)
Functional Patterns (3)
Golden Model (3)
HLV (3)
Hardware Architecture (3)
Hardware Assurance (3)
Horizontal Reuse (3)
Illegal Bins (3)
Integrity Challenges (3)
Intelligent Integration (3)
JUnit (3)
July 2023 - Volume 19 Issue 2 (3)
Jump Statements (3)
Lane Margining (3)
Level-shifter (3)
Load Balancing (3)
Loggers (3)
Loop Statements (3)
MC2 (3)
MUX (3)
Mailboxes (3)
Mathematical Analysis (3)
Memory Debug (3)
Method (3)
NRRs (3)
NoC (3)
OSVVM (3)
Observability (3)
Observer (3)
Open Architecture (3)
Operating State (3)
PCI-SIG (3)
Package Organization (3)
Parallel Computing (3)
Phase-Level (3)
Polymorphic Behavior (3)
Power Architecture (3)
Power Consumption (3)
Power Gating (3)
Property Assist (3)
Protocol Layers (3)
QFL (3)
Qrun (3)
Quality Assurance (3)
RISC-V Verification Interface (3)
RTL Emulation (3)
Radiation Mitigation (3)
Re-targeting (3)
Real Number Modeling (3)
Regime (3)
Register Assistant (3)
Register-Level Stimulus (3)
Retimers (3)
Routines (3)
SDC (3)
SDC Verification (3)
Safety Assurance (3)
Scripting (3)
Security Coverage (3)
Security Vulnerabilities (3)
Semaphores (3)
Sign-Off Methodology (3)
Signal Property (3)
Signal-Level (3)
Single Step Debug (3)
Singleton (3)
Slave Agent (3)
Soft Reset (3)
Source Code Management (3)
Specification Driven Formal (3)
Spiral Refinement (3)
State Transition (3)
Static Lists (3)
Static Properties (3)
System Confidence (3)
System Verification (3)
TBX (3)
TDISP (3)
Task Call (3)
Test Realization (3)
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Transaction Layer (3)
Transitive (3)
Type Casting (3)
Typedef (3)
UEFI (3)
iTBA (3)
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