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Effective Elements Lists and the Transitive Nature of UPF Commands

Article - Feb 25, 2019 Progyna Khondkar

In this article, we provide a simplistic approach to find inherent links between UPF commands-options through their transitive nature. We also explain how these inherent features help to foster and establish exact relationships between UPF and DUT objects in order to develop UPF for power management and implementation as well as conduct power aware verification.
Selecting a Portable Stimulus Application Focal Point

Article - Feb 25, 2019 Matthew Ballance

As designs, especially System on Chip designs, have become more complex, the need for generated good, automated stimulus across the verification spectrum has increased. Today, the need for verification reuse and automated stimulus is clearly seen from block to subsystem to SoC-level verification.
Choosing a Format for the Portable Stimulus Specification

Resource (Paper (.PDF)) - Feb 22, 2019 Matthew Ballance

This white paper discusses portable stimulus, the industry’s solution for verification portability up and down the design hierarchy and across platforms.
Part 10: IC/ASIC Language and Library Adoption Trends

Resource (Verification Horizons Blog) - Feb 14, 2019 Harry Foster

In my previous blog ( click here ), I examined IC/ASIC project verification technology adoption trends. In this blog I plan to discuss various IC/ASIC language and library adoption trends.
Part 9: IC/ASIC Verification Technology Adoption Trends

Resource (Verification Horizons Blog) - Feb 05, 2019 Harry Foster

In my previous blog ( click here ), I focused on IC/ASIC design project resource trends. In this blog I examine IC/ASIC project verification technology adoption trends.
Low Power Verification Forum

Webinar - Feb 05, 2019 Gordon Allan

In this session, you will be introduced to new and unique low power coverage methodologies that enable designers to verify and track how well they have tested their power management architecture.
Part 8: IC/ASIC Resource Trends

Resource (Verification Horizons Blog) - Jan 29, 2019 Harry Foster

In my previous blog ( click here ), I presented trends related to various aspects of design to illustrate growing design complexity. In this blog, I plan to discuss the growing IC/ASIC project resource trends resulting from growing design complexity.
Industry Advancements Required to Close the Power Management Verification Gap

Webinar - Jan 28, 2019 Sriram Hariharan

In this session, you will learn how Qualcomm overcomes their power verification challenges and how they utilize power aware verification techniques.
Deploying a Metrics Driven Low Power Methodology for Your RTL IP

Webinar - Jan 28, 2019 Qazi Ahmed

In this session, you will learn how PowerPro is a single solution for RTL audit, power optimization, estimation and exploration.
Low Power Verification & Analysis with Emulation

Webinar - Jan 28, 2019 Shantanu Samant

In this session, you will learn how Emulation techniques can be used for low power verification including power analysis and power estimation.
Productive Low Power Debug Across All Engines and Flows

Webinar - Jan 28, 2019 Gordon Allan

In this session, we will answer the top nine questions asked for debugging low power in your design.
Accelerating Verification through Verification IP, Configurator and UVM Framework

Resource (Slides (.PDF)) - Jan 24, 2019 Sharath Kannareddy
Making Verification Fun Again

Resource (Slides (.PDF)) - Jan 24, 2019 Jonathan Craft
Verification Acceleration for FPGA Designs with Matlab

Resource (Slides (.PDF)) - Jan 24, 2019 Jerry Grula - Siemens EDA
Welcome & Overview

Resource (Slides (.PDF)) - Jan 24, 2019 Harry Foster
ASIC & FPGA SoC Functional Verification Trends

Resource (Slides (.PDF)) - Jan 24, 2019 Harry Foster
Part 7: IC/ASIC Design Trends

Resource (Verification Horizons Blog) - Jan 22, 2019 Harry Foster

In my previous blog ( click here ), I focused on FPGA design and verification trends. Now my plan is to shift the focus in this series of blogs from FPGA trends to IC/ASIC trends. And specifically in this blog, I present trends related to various aspects of design to illustrate growing design complexity.
Part 6: FPGA Verification Language and Library Adoption Trends

Resource (Verification Horizons Blog) - Jan 15, 2019 Harry Foster

In my previous blog ( click here ) I discussed FPGA verification techniques and technologies adoption trends, as identified by the 2018 WRG study. In this blog, I’ll present FPGA design and verification language adoption trends. It is not uncommon for FPGA projects to use multiple languages when constructing their RTL and testbenches. This practice is often due to legacy code as well as purchased IP.
Part 5: FPGA Verification Technology Adoption Trends

Resource (Verification Horizons Blog) - Jan 07, 2019 Harry Foster

In my previous blog ( click here ) I discussed verification effort trends specifically focused on where FPGA design and verification engineers spend their time. In this blog I present verification techniques and technologies adoption trends, as identified by the 2018 Wilson Research Group study.
Part 4: FPGA Verification Effort Trends (Continued)

Resource (Verification Horizons Blog) - Jan 02, 2019 Harry Foster

In my previous blog ( click here ) I discussed verification effort trends in terms of project time spent in verification, as well as increasing headcount as indicated by the rising mean peak number of design and verification engineers working on FPGA projects. In this blog I continue the discussion of FPGA verification effort trends by looking at where engineers spend their time.
How to Unearth Deep Bugs Faster and Cheaper Using Formal Bug Hunting Techniques

Webinar - Dec 23, 2018 Mark Eslinger

In this session, you will learn how to leverage formal analysis to find and fix as many functional bugs as possible, ultimately improving the quality of your end-product, and lowering the risk of re-spins.
Effective Elements List and Transitive Natures of UPF Commands

Resource (Paper (.PDF)) - Dec 21, 2018 Progyna Khondkar

It is evident now that UPF commands-options are inherently transitive in nature through the implicit or explicit – transitive option. With the progression of UPF versions and revisions from UPF 2.0 to 2.1 and onward, the transitive nature becomes more realistic and consistent with all UPF semantics, specifically for UPF strategies, as well as for UPF and DUT objects.
Effective Elements List and Transitive Natures of UPF Commands

Paper - Dec 21, 2018 Progyna Khondkar

The UPF commands are, in general, transitive in nature. For example, for any given instance included in a power domain, all child instances of that given instance are transitively included in the power domain, unless any child instance is explicitly excluded from this particular power domain or is explicitly included in the definition of another power domain.
Full-Featured SOC Debug Cross-Triggering

Article - Dec 10, 2018 Verification Methodology Team
Part 3: FPGA Verification Effort Trends

Resource (Verification Horizons Blog) - Dec 04, 2018 Harry Foster

This blog is a continuation of a series of blogs related to the 2018 Wilson Research Group Functional Verification Study ( click here ). In my previous blog ( click here ), I presented the findings from our new study related to how successful FPGA projects are in terms of verification effectiveness. In this blog I focus on FPGA verification effort trends.