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    Author: Eric Rentschler - Mentor Graphics Abstract: As chip design complexity has grown, there are now many off-the-shelf and proprietary tools in-use across the in-dustry for on-chip debug logic. These solutions span both the FPGA prototyping and ASIC spaces. Because many of today's challenging debug problems arise at the SoC level, debug capabilities across multiple IP blocks is critical. The ability to easily cross-trigger between debug engines across the entire system is achieved here. This paper ad-dresses key cross triggering characteristics. These capabilities are demonstrated in the Mentor Graphics Certus de-bug solution on an ARM design. Flexible cross-triggering provides a rich set of capabilities for efficient and power-ful validation/debug cycle time. View & Download: Read the entire Full-Featured SOC Debug Cross-Triggering poster paper. Source: DAC 2016