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Understanding and Minimizing Study Bias (2020 Study)

Resource (Verification Horizons Blog) - Oct 30, 2020 Harry Foster

This blog is a continuation on the 2020 Wilson Research Group Functional Verification Study blog series. A big concern when architecting any type of study relates to addressing three types of bias: non-response bias, sample validity bias, and stakeholder bias. In this blog I point out where potential biases might occur in our study, and multiple techniques we adopted to minimize these biases.
ISO 26262 Fault Campaign Management

Resource (Slides (.PDF)) - Oct 29, 2020 Jacob Wiltgen
ISO 26262: Fault Campaign Management

Session - Oct 29, 2020 Jake Wiltgen

In this session, you will gain an understanding of the core challenges executing an ISO 26262 Fault Campaign and a methodology to ensure maximum efficiency. This session will describe the pros and cons of solutions contributing to the closure of a fault campaign. Additionally, a workflow and methodology will be defined which enables maximum efficiency in closing out the fault campaign.
Prologue: The 2020 Wilson Research Group Functional Verification Study

Resource (Verification Horizons Blog) - Oct 27, 2020 Harry Foster

This is the first in a sequence of blogs that presents the findings from our new 2020 Wilson Research Group Functional Verification Study. Similar to my previous 2018 WRG functional verification study blog series , I plan to separate the discussion by FPGA and IC/ASIC findings. Study Overview The study results presented in this blog series are a continuation of a series of industry studies on functional verification that began in 2007 and continued biennially starting in 2010 through 2020.
Interactive Debug Techniques for UVM, SystemVerilog and RTL using Visualizer

Webinar - Oct 27, 2020 Jason Polychronopoulos

Debug is one of the most time-consuming tasks verification engineers face in the design and verification of FPGAs, IPs and SoCs. Visualizer provides an advanced debug environment that includes many tools to help with both post-simulation and live-simulation debug. This session will cover different techniques for debugging SystemVerilog UVM testbench and RTL source code while running a live simulation.
Quantifying FPGA Verification Effectiveness

Article - Oct 26, 2020 Harry Foster

The 2019 global semiconductor market was valued at $385.4 billion after experiencing a 15% decline due to a 32% drop in the memory IC market, which is expected to recover in 2021 [1] . The FPGA portion of the semiconductor market is valued at about $5 billion [2] . The FPGA semiconductor market is expected to reach a value of $7.5 billion by 2030, growing at a compounded annual growth rate (CAGR) of 4.4% during this forecast period.
Arasan MIPI® CSI-2-RX IP Verification Using Questa Verification IPs

Article - Oct 26, 2020 Vikas Sharma - Siemens EDA

This article describes the verification process of the ARASAN MIPI® CSI-2-RX IP core using Questa Verification IPs.
Memory Softmodels - The Foundation of Validation Accuracy

Article - Oct 26, 2020 Ridham Kothari - Siemens EDA

As always, we must continue to reduce the time-to-market of SoCs and complex systems. An FPGA prototype implementation of these systems can be used as a basis for early software or firmware development, hardware-software co-verification and system validation, and all this can be achieved before actual silicon is available.
Increasing Functional Coverage by Automation for Zetta-Hz High Speed CDMA Transceiver

Article - Oct 26, 2020 Karthik Bandaru, Priyanka Gharat, and Sastry Puranapanda - Silicon Interfaces®

The efforts to apply constrained randomization to create test cases is based on the developer or verification engineer’s perception of what test vectors are required and can easily lead to hidden bugs being overlooked. Traditionally, the coverage goals would have been reached by writing more test cases with unpredictable schedules, often impacting time-to-market goals. Functional coverage defines critical states and constrained randomization tests those states in unpredictable ways.
Unified Approach to Verify Complex FSM

Article - Oct 26, 2020 Milan Patel - eInfochips, LTD (an Arrow Company)

The purpose of this article is to share a strategy on how to verify any simple or complex FSM in an organized, robust, manageable, and efficient way. To verify such FSMs thoroughly we need random scenarios that cover all the possible state transition conditions, corner and boundary conditions, and relevant functional behavior. For that, we require a strong base entity that helps to generate random scenarios to cover all FSM entry-exit conditions and erroneous scenarios easily.
RISC-V Design Verification Strategy

Article - Oct 26, 2020 Dr. Mike Bartley

As the RISC-V architecture becomes increasingly popular, it is being adopted across a diverse range of products. From the development of in-house cores with specialized instructions, to functionally safe SoCs and security processors for a variety of verticals – RISC-V adoption brings several verification challenges that are discussed in this article, along with potential approaches and solutions.
Reducing Area & Power Consumption with Formal-based ‘X’ Verification

Webinar - Oct 15, 2020 Ping Yeung

In this session we will share a comprehensive static and formal-based methodology employing this app that enables design teams to root cause ‘X’ issues early in the RTL design process.
FPGA Functional Verification Trend Report - 2020

Paper - Oct 13, 2020 Harry Foster

This report presents the results from the 2020 Wilson Research Group Functional Verification Study focused on the Field-Programmable Gate Array (FPGA) segment. The findings from this study provide invaluable insight into the state of today’s FPGA market in terms of both design and verification trends.
FPGA Functional Verification Trend Report - 2020

Resource (Paper (.PDF)) - Oct 13, 2020 Harry Foster

This report examines the trends in functional verification for the field programmable gate array (FPGA) market segments identified in the 2020 Wilson Research Group study.
IC/ASIC Functional Verification Trend Report - 2020

Resource (Paper (.PDF)) - Oct 13, 2020 Harry Foster

This report examines the trends in functional verification for integrated circuits (ICs) and application-specific integrated circuits (ASICs) as identified in the 2020 Wilson Research Group study.
IC/ASIC Functional Verification Trend Report - 2020

Paper - Oct 13, 2020 Harry Foster

This report presents the results from the 2020 Wilson Research Group functional verification study, which were focused on the integrated circuit (IC) and application specific integrated circuit (ASIC) market segments. The findings from this study provide invaluable insight into the state of today’s IC/ASIC market in terms of both design and verification trends.
Functional Verification Study - 2020

Session - Oct 13, 2020 Harry Foster

In this session, Harry Foster highlights the key findings from the 2020 Wilson Research Group Functional Verification Study, and provides his interpretation and analysis behind today's emerging trends.
Stimulating Simulating 2: UVM Sequences

Webinar - Oct 08, 2020 Chris Spear

In this session, you will learn more about UVM Sequences; creating classes, transactions flow and virtual sequences. In addition, Chris will share best practices with UVM sequence classes.
ISO 26262 Bottoms-Up Safety Analysis

Resource (Slides (.PDF)) - Sep 29, 2020 Jacob Wiltgen
ISO 26262: Bottoms-Up Safety Analysis

Session - Sep 29, 2020 Jake Wiltgen

In this session, you will gain an understanding of the core challenges performing safety analysis in today’s complex IP and IC architectures. This session will describe the impact to inaccurate analysis and how bottoms-up safety analysis is critical to ensuring an efficient single iteration safety lifecycle. A workflow and methodology defining the approach to bottoms-up safety analysis is described.
Should I Kill My Formal Run? Part 2: Avoid Trouble and Set Yourself Up For Success

Webinar - Sep 01, 2020 Jin Hou

In this session we assume you are about to kick off a formal analysis, and want to make sure you will avoid the most obvious pitfalls in setting up your formal testbench, the DUT, and the runner scripting.
Stimulating Simulating: UVM Transactions

Webinar - Aug 26, 2020 Chris Spear

In this session, you will learn how to create classes for UVM transactions, also known as sequence items. You will also be shown how to add new functionality to a transaction, by extending the class and much more.
Verilog Basics for SystemVerilog Constrained Random Verification

Webinar - Aug 18, 2020 Dave Rich

In this session we will review two of the most common issues when constraint solver results do not match your intent: 1) not understanding how Verilog expression evaluation rules apply to interpret the rules of basic algebra, and 2) not understanding the affect probability has on choosing solution values.
Formal is the New Normal - Deploy These FV Apps in Your Next Project

Article - Jul 19, 2020 Ajeetha Kumari, Hemamalini Sundaram, and Darshan Ballari, VerifWorks, LLC and CVC Pvt., Ltd.

Formal verification is now pervasive in many chip design verification projects. Key to this widespread adoption is the availability of automated “apps” that makes it easy to deploy Formal in hitherto simulation-only projects. We at VerifWorks have a long history of formal deployment at many design houses and have seen the challenges engineers face while adopting the same. We have also trained hundreds of engineers to use Formal with ABV (Assertion-Based Verification) through CVC.
Understanding the SVA Engine Using the Fork-Join Model

Article - Jul 19, 2020 Ben Cohen

SVA ( SystemVerilog Assertions ) is a powerful short-handed assertion language with many constructs; it is built as an integral part of SystemVerilog but with a specific syntax and sets of rules. Unlike a scoreboard that tends to focus on a model implementation that mimics the DUT, SVA addresses the requirements; that brings out a better understanding of the requirements, along with its weaknesses for lack of definitions.