New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Download 2023.4_2

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Verification Horizons Blog

Upcoming VIQ Webinar

Thursday, Nov 21st-8:00 AM PST

Boost Your Verification Productivity with Questa Verification IQ

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On-Demand HBM4 Webinar

Verifying the Next Generation High Bandwidth Memory Controllers for AI and HPC Applications

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Upcoming FPU Webinar

Wednesday, Jan 22nd-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

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SIEMENS Verification Academy

Stephen Bailey

As Director of Emerging Technologies, Stephen Bailey seeks out and develops new technology, solutions and business opportunities in functional verification and related areas. He brings many years of industry experience working in R&D, applications and technical and product marketing. He has contributed to the industry through participation in industry standards, including chairing VHDL (IEEE 1076) and UPF (IEEE 1801) working groups, and serving in various roles from member of technical program committee to conference chair with conferences such as DVCon. Prior to joining the EDA industry, Steve developed embedded software and software development tools. Steve has BS and MS degrees in computer science from Chapman University.

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