New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Download 2023.4_2

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Verification Horizons Blog

Upcoming VIQ Webinar

Thursday, Nov 21st-8:00 AM PST

Boost Your Verification Productivity with Questa Verification IQ

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On-Demand HBM4 Webinar

Verifying the Next Generation High Bandwidth Memory Controllers for AI and HPC Applications

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Upcoming FPU Webinar

Wednesday, Jan 22nd-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

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SIEMENS Verification Academy

Nicolae Tusinschi

Nicolae Tusinschi is a product manager for formal verification solutions at Siemens EDA. He holds a master’s degree combined between the University of Southampton and the University of Kaiserslautern. After a master’s thesis at Continental, Nicolae joined OneSpin, where he worked in QA, then as a product specialist and later served as product owner for design verification tools at OneSpin. His key projects include integrating simulation coverage with formal metrics, leveraging coverage results in the verification process, formal verification of RISC-V cores.

Content by Nicolae Tusinschi

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