New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Download 2023.4_2

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Verification Horizons Blog

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Thursday, Nov 21st-8:00 AM PST

Boost Your Verification Productivity with Questa Verification IQ

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On-Demand HBM4 Webinar

Verifying the Next Generation High Bandwidth Memory Controllers for AI and HPC Applications

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Wednesday, Jan 22nd-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

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SIEMENS Verification Academy

Ahmed Eisawy

Ahmed Eisawy is a member of the Technical & Product Marketing team of the Analog/Mixed-Signal group – part of the Deep Sub-micron Division – at Siemens EDA. For the last five years, he’s been working as a member of the marketing team to drive the development of Analog/Mixed-Signal simulators forward with new technologies as well as engage with customers for evaluations, training & education, solving complex problems as well as help the customers through methodology assessments to improve their flow. Previously, Ahmed worked for seven years in technical support where he worked closely with customers, helping resolve problems and help formulate the customer needs into tool enhancements. He received his BSEE from Cairo University in 1999 and his MSEE from the same university in 2002.

Content by Ahmed Eisawy

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